uart_lcd.hier_info

结合了SOPC的精髓的串口通信程序实现功能很好

|uart_lcd
RS <= lcd_driver:inst1.rs
clk => counter2:inst3.clk
clk => counter1:inst2.clk
reset => inst4.IN0
uart_rxd => reciver:inst.rxdr
RW <= lcd_driver:inst1.rw
EN <= lcd_driver:inst1.en
D[0] <= lcd_driver:inst1.data[0]
D[1] <= lcd_driver:inst1.data[1]
D[2] <= lcd_driver:inst1.data[2]
D[3] <= lcd_driver:inst1.data[3]
D[4] <= lcd_driver:inst1.data[4]
D[5] <= lcd_driver:inst1.data[5]
D[6] <= lcd_driver:inst1.data[6]
D[7] <= lcd_driver:inst1.data[7]


|uart_lcd|lcd_driver:inst1
clk => data[7]~reg0.CLK
clk => data[6]~reg0.CLK
clk => data[5]~reg0.CLK
clk => data[4]~reg0.CLK
clk => data[3]~reg0.CLK
clk => data[2]~reg0.CLK
clk => data[1]~reg0.CLK
clk => data[0]~reg0.CLK
clk => datacnt[2].CLK
clk => datacnt[1].CLK
clk => datacnt[0].CLK
clk => high_buffer[3].CLK
clk => high_buffer[2].CLK
clk => high_buffer[1].CLK
clk => high_buffer[0].CLK
clk => high_integer[3].CLK
clk => high_integer[2].CLK
clk => high_integer[1].CLK
clk => high_integer[0].CLK
clk => low_buffer[3].CLK
clk => low_buffer[2].CLK
clk => low_buffer[1].CLK
clk => low_buffer[0].CLK
clk => low_integer[3].CLK
clk => low_integer[2].CLK
clk => low_integer[1].CLK
clk => low_integer[0].CLK
clk => rs~reg0.CLK
clk => en.DATAIN
clk => state~10.IN1
ready => receive_buffer[6].CLK
ready => receive_buffer[5].CLK
ready => receive_buffer[4].CLK
ready => receive_buffer[3].CLK
ready => receive_buffer[2].CLK
ready => receive_buffer[1].CLK
ready => receive_buffer[0].CLK
ready => receive_buffer[7].CLK
datain[0] => receive_buffer[0].DATAIN
datain[1] => receive_buffer[1].DATAIN
datain[2] => receive_buffer[2].DATAIN
datain[3] => receive_buffer[3].DATAIN
datain[4] => receive_buffer[4].DATAIN
datain[5] => receive_buffer[5].DATAIN
datain[6] => receive_buffer[6].DATAIN
datain[7] => receive_buffer[7].DATAIN
rs <= rs~reg0.DB_MAX_OUTPUT_PORT_TYPE
rw <= <GND>
en <= clk.DB_MAX_OUTPUT_PORT_TYPE
data[0] <= data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[1] <= data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[2] <= data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[3] <= data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[4] <= data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[5] <= data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[6] <= data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[7] <= data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|uart_lcd|counter2:inst3
clk => cnt1[13].CLK
clk => cnt1[12].CLK
clk => cnt1[11].CLK
clk => cnt1[10].CLK
clk => cnt1[9].CLK
clk => cnt1[8].CLK
clk => cnt1[7].CLK
clk => cnt1[6].CLK
clk => cnt1[5].CLK
clk => cnt1[4].CLK
clk => cnt1[3].CLK
clk => cnt1[2].CLK
clk => cnt1[1].CLK
clk => cnt1[0].CLK
clk => bc.CLK
bclk <= bclk~reg0.DB_MAX_OUTPUT_PORT_TYPE


|uart_lcd|reciver:inst
bclkr => \pro2:count[3].CLK
bclkr => \pro2:count[2].CLK
bclkr => \pro2:count[1].CLK
bclkr => \pro2:count[0].CLK
bclkr => r_ready~reg0.CLK
bclkr => \pro2:rcnt[31].CLK
bclkr => \pro2:rcnt[30].CLK
bclkr => \pro2:rcnt[29].CLK
bclkr => \pro2:rcnt[28].CLK
bclkr => \pro2:rcnt[27].CLK
bclkr => \pro2:rcnt[26].CLK
bclkr => \pro2:rcnt[25].CLK
bclkr => \pro2:rcnt[24].CLK
bclkr => \pro2:rcnt[23].CLK
bclkr => \pro2:rcnt[22].CLK
bclkr => \pro2:rcnt[21].CLK
bclkr => \pro2:rcnt[20].CLK
bclkr => \pro2:rcnt[19].CLK
bclkr => \pro2:rcnt[18].CLK
bclkr => \pro2:rcnt[17].CLK
bclkr => \pro2:rcnt[16].CLK
bclkr => \pro2:rcnt[15].CLK
bclkr => \pro2:rcnt[14].CLK
bclkr => \pro2:rcnt[13].CLK
bclkr => \pro2:rcnt[12].CLK
bclkr => \pro2:rcnt[11].CLK
bclkr => \pro2:rcnt[10].CLK
bclkr => \pro2:rcnt[9].CLK
bclkr => \pro2:rcnt[8].CLK
bclkr => \pro2:rcnt[7].CLK
bclkr => \pro2:rcnt[6].CLK
bclkr => \pro2:rcnt[5].CLK
bclkr => \pro2:rcnt[4].CLK
bclkr => \pro2:rcnt[3].CLK
bclkr => \pro2:rcnt[2].CLK
bclkr => \pro2:rcnt[1].CLK
bclkr => \pro2:rcnt[0].CLK
bclkr => \pro2:rbufs[7].CLK
bclkr => \pro2:rbufs[6].CLK
bclkr => \pro2:rbufs[5].CLK
bclkr => \pro2:rbufs[4].CLK
bclkr => \pro2:rbufs[3].CLK
bclkr => \pro2:rbufs[2].CLK
bclkr => \pro2:rbufs[1].CLK
bclkr => \pro2:rbufs[0].CLK
bclkr => rbuf[7]~reg0.CLK
bclkr => rbuf[6]~reg0.CLK
bclkr => rbuf[5]~reg0.CLK
bclkr => rbuf[4]~reg0.CLK
bclkr => rbuf[3]~reg0.CLK
bclkr => rbuf[2]~reg0.CLK
bclkr => rbuf[1]~reg0.CLK
bclkr => rbuf[0]~reg0.CLK
bclkr => state~8.IN1
resetr => \pro2:count[3].ACLR
resetr => \pro2:count[2].ACLR
resetr => \pro2:count[1].ACLR
resetr => \pro2:count[0].ACLR
resetr => r_ready~reg0.ENA
resetr => \pro2:rcnt[31].ENA
resetr => \pro2:rcnt[30].ENA
resetr => \pro2:rcnt[29].ENA
resetr => \pro2:rcnt[28].ENA
resetr => \pro2:rcnt[27].ENA
resetr => \pro2:rcnt[26].ENA
resetr => \pro2:rcnt[25].ENA
resetr => \pro2:rcnt[24].ENA
resetr => \pro2:rcnt[23].ENA
resetr => \pro2:rcnt[22].ENA
resetr => \pro2:rcnt[21].ENA
resetr => \pro2:rcnt[20].ENA
resetr => \pro2:rcnt[19].ENA
resetr => \pro2:rcnt[18].ENA
resetr => \pro2:rcnt[17].ENA
resetr => \pro2:rcnt[16].ENA
resetr => \pro2:rcnt[15].ENA
resetr => \pro2:rcnt[14].ENA
resetr => \pro2:rcnt[13].ENA
resetr => \pro2:rcnt[12].ENA
resetr => \pro2:rcnt[11].ENA
resetr => \pro2:rcnt[10].ENA
resetr => \pro2:rcnt[9].ENA
resetr => \pro2:rcnt[8].ENA
resetr => \pro2:rcnt[7].ENA
resetr => \pro2:rcnt[6].ENA
resetr => \pro2:rcnt[5].ENA
resetr => \pro2:rcnt[4].ENA
resetr => \pro2:rcnt[3].ENA
resetr => \pro2:rcnt[2].ENA
resetr => \pro2:rcnt[1].ENA
resetr => \pro2:rcnt[0].ENA
resetr => state~9.IN1
rxdr => Select~0.IN6
rxdr => Select~0.IN7
rxdr => state~0.OUTPUTSELECT
rxdr => Select~1.IN1
rxdr => rcnt~0.OUTPUTSELECT
rxdr => rcnt~1.OUTPUTSELECT
rxdr => rcnt~2.OUTPUTSELECT
rxdr => rcnt~3.OUTPUTSELECT
rxdr => rcnt~4.OUTPUTSELECT
rxdr => rcnt~5.OUTPUTSELECT
rxdr => rcnt~6.OUTPUTSELECT
rxdr => rcnt~7.OUTPUTSELECT
rxdr => rcnt~8.OUTPUTSELECT
rxdr => rcnt~9.OUTPUTSELECT
rxdr => rcnt~10.OUTPUTSELECT
rxdr => rcnt~11.OUTPUTSELECT
rxdr => rcnt~12.OUTPUTSELECT
rxdr => rcnt~13.OUTPUTSELECT
rxdr => rcnt~14.OUTPUTSELECT
rxdr => rcnt~15.OUTPUTSELECT
rxdr => rcnt~16.OUTPUTSELECT
rxdr => rcnt~17.OUTPUTSELECT
rxdr => rcnt~18.OUTPUTSELECT
rxdr => rcnt~19.OUTPUTSELECT
rxdr => rcnt~20.OUTPUTSELECT
rxdr => rcnt~21.OUTPUTSELECT
rxdr => rcnt~22.OUTPUTSELECT
rxdr => rcnt~23.OUTPUTSELECT
rxdr => rcnt~24.OUTPUTSELECT
rxdr => rcnt~25.OUTPUTSELECT
rxdr => rcnt~26.OUTPUTSELECT
rxdr => rcnt~27.OUTPUTSELECT
rxdr => rcnt~28.OUTPUTSELECT
rxdr => rcnt~29.OUTPUTSELECT
rxdr => rcnt~30.OUTPUTSELECT
rxdr => rcnt~31.OUTPUTSELECT
rxdr => state~1.OUTPUTSELECT
rxdr => count~4.OUTPUTSELECT
rxdr => count~5.OUTPUTSELECT
rxdr => count~6.OUTPUTSELECT
rxdr => count~7.OUTPUTSELECT
rxdr => \pro2:rbufs[7].DATAIN
rxdr => \pro2:rbufs[6].DATAIN
rxdr => \pro2:rbufs[5].DATAIN
rxdr => \pro2:rbufs[4].DATAIN
rxdr => \pro2:rbufs[3].DATAIN
rxdr => \pro2:rbufs[2].DATAIN
rxdr => \pro2:rbufs[1].DATAIN
rxdr => \pro2:rbufs[0].DATAIN
r_ready <= r_ready~reg0.DB_MAX_OUTPUT_PORT_TYPE
rbuf[0] <= rbuf[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rbuf[1] <= rbuf[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rbuf[2] <= rbuf[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rbuf[3] <= rbuf[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rbuf[4] <= rbuf[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rbuf[5] <= rbuf[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rbuf[6] <= rbuf[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rbuf[7] <= rbuf[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|uart_lcd|counter1:inst2
clk => \main:clk_count[12].CLK
clk => \main:clk_count[11].CLK
clk => \main:clk_count[10].CLK
clk => \main:clk_count[9].CLK
clk => \main:clk_count[8].CLK
clk => \main:clk_count[7].CLK
clk => \main:clk_count[6].CLK
clk => \main:clk_count[5].CLK
clk => \main:clk_count[4].CLK
clk => \main:clk_count[3].CLK
clk => \main:clk_count[2].CLK
clk => \main:clk_count[1].CLK
clk => \main:clk_count[0].CLK
clk => bd_out~reg0.CLK
reset => \main:clk_count[12].ACLR
reset => \main:clk_count[11].ACLR
reset => \main:clk_count[10].ACLR
reset => \main:clk_count[9].ACLR
reset => \main:clk_count[8].ACLR
reset => \main:clk_count[7].ACLR
reset => \main:clk_count[6].ACLR
reset => \main:clk_count[5].ACLR
reset => \main:clk_count[4].ACLR
reset => \main:clk_count[3].ACLR
reset => \main:clk_count[2].ACLR
reset => \main:clk_count[1].ACLR
reset => \main:clk_count[0].ACLR
reset => bd_out~reg0.ACLR
bd_out <= bd_out~reg0.DB_MAX_OUTPUT_PORT_TYPE