uart_lcd.fit.qmsg

结合了SOPC的精髓的串口通信程序实现功能很好

{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "reciver:inst\|r_ready  " "Info: Automatically promoted node reciver:inst\|r_ready " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "reciver:inst\|Select~534 " "Info: Destination node reciver:inst\|Select~534" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "reciver:inst\|Select~534" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "" { reciver:inst|Select~534 } "NODE_NAME" } "" } } { "E:/myproject/uart_lcd/uart_lcd.fld" "" { Floorplan "E:/myproject/uart_lcd/uart_lcd.fld" "" "" { reciver:inst|Select~534 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0}  } { { "reciver.vhd" "" { Text "E:/myproject/uart_lcd/reciver.vhd" 9 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "reciver:inst\|r_ready" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "" { reciver:inst|r_ready } "NODE_NAME" } "" } } { "E:/myproject/uart_lcd/uart_lcd.fld" "" { Floorplan "E:/myproject/uart_lcd/uart_lcd.fld" "" "" { reciver:inst|r_ready } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "counter2:inst3\|bc  " "Info: Automatically promoted node counter2:inst3\|bc " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "counter2:inst3\|bc~88 " "Info: Destination node counter2:inst3\|bc~88" {  } { { "counter2.vhd" "" { Text "E:/myproject/uart_lcd/counter2.vhd" 12 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "counter2:inst3\|bc~88" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "" { counter2:inst3|bc~88 } "NODE_NAME" } "" } } { "E:/myproject/uart_lcd/uart_lcd.fld" "" { Floorplan "E:/myproject/uart_lcd/uart_lcd.fld" "" "" { counter2:inst3|bc~88 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0}  } { { "counter2.vhd" "" { Text "E:/myproject/uart_lcd/counter2.vhd" 12 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "counter2:inst3\|bc" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "" { counter2:inst3|bc } "NODE_NAME" } "" } } { "E:/myproject/uart_lcd/uart_lcd.fld" "" { Floorplan "E:/myproject/uart_lcd/uart_lcd.fld" "" "" { counter2:inst3|bc } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Performing register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Completed register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0 0 "Started Fast Input/Output/OE register processing" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0 0 "Finished Fast Input/Output/OE register processing" 0 0}
{ "Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 0 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0 0 "Finished register packing" 0 0}