uart_lcd.fit.qmsg

结合了SOPC的精髓的串口通信程序实现功能很好

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 04 22:54:25 2007 " "Info: Processing started: Tue Dec 04 22:54:25 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off uart_lcd -c uart_lcd " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off uart_lcd -c uart_lcd" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "uart_lcd EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"uart_lcd\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk (placed in PIN 23 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node clk (placed in PIN 23 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0}  } { { "uart_lcd.bdf" "" { Schematic "E:/myproject/uart_lcd/uart_lcd.bdf" { { 72 -24 144 88 "clk" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "" { clk } "NODE_NAME" } "" } } { "E:/myproject/uart_lcd/uart_lcd.fld" "" { Floorplan "E:/myproject/uart_lcd/uart_lcd.fld" "" "" { clk } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "counter1:inst2\|bd_out  " "Info: Automatically promoted node counter1:inst2\|bd_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "counter1:inst2\|bd_out~84 " "Info: Destination node counter1:inst2\|bd_out~84" {  } { { "counter1.vhd" "" { Text "E:/myproject/uart_lcd/counter1.vhd" 8 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "counter1:inst2\|bd_out~84" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "" { counter1:inst2|bd_out~84 } "NODE_NAME" } "" } } { "E:/myproject/uart_lcd/uart_lcd.fld" "" { Floorplan "E:/myproject/uart_lcd/uart_lcd.fld" "" "" { counter1:inst2|bd_out~84 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0}  } { { "counter1.vhd" "" { Text "E:/myproject/uart_lcd/counter1.vhd" 8 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "counter1:inst2\|bd_out" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "" { counter1:inst2|bd_out } "NODE_NAME" } "" } } { "E:/myproject/uart_lcd/uart_lcd.fld" "" { Floorplan "E:/myproject/uart_lcd/uart_lcd.fld" "" "" { counter1:inst2|bd_out } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "counter2:inst3\|bclk  " "Info: Automatically promoted node counter2:inst3\|bclk " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "EN " "Info: Destination node EN" {  } { { "uart_lcd.bdf" "" { Schematic "E:/myproject/uart_lcd/uart_lcd.bdf" { { 168 848 1024 184 "EN" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "EN" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "" { EN } "NODE_NAME" } "" } } { "E:/myproject/uart_lcd/uart_lcd.fld" "" { Floorplan "E:/myproject/uart_lcd/uart_lcd.fld" "" "" { EN } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "counter2:inst3\|bclk~61 " "Info: Destination node counter2:inst3\|bclk~61" {  } { { "counter2.vhd" "" { Text "E:/myproject/uart_lcd/counter2.vhd" 7 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "counter2:inst3\|bclk~61" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "" { counter2:inst3|bclk~61 } "NODE_NAME" } "" } } { "E:/myproject/uart_lcd/uart_lcd.fld" "" { Floorplan "E:/myproject/uart_lcd/uart_lcd.fld" "" "" { counter2:inst3|bclk~61 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0}  } { { "counter2.vhd" "" { Text "E:/myproject/uart_lcd/counter2.vhd" 7 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "counter2:inst3\|bclk" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "" { counter2:inst3|bclk } "NODE_NAME" } "" } } { "E:/myproject/uart_lcd/uart_lcd.fld" "" { Floorplan "E:/myproject/uart_lcd/uart_lcd.fld" "" "" { counter2:inst3|bclk } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}