uart_lcd.tan.qmsg

串口通信的事例FPGA上面可以实现非常实用

{ "Info" "ITDB_FULL_TCO_RESULT" "clk D\[7\] lcd_driver:inst1\|data\[7\] 13.645 ns register " "Info: tco from clock \"clk\" to destination pin \"D\[7\]\" through register \"lcd_driver:inst1\|data\[7\]\" is 13.645 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.785 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.785 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "" { clk } "NODE_NAME" } "" } } { "uart_lcd.bdf" "" { Schematic "E:/myproject/uart_lcd/uart_lcd.bdf" { { 72 -24 144 88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.269 ns clk~clkctrl 2 COMB CLKCTRL_G2 29 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.269 ns; Loc. = CLKCTRL_G2; Fanout = 29; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "uart_lcd.bdf" "" { Schematic "E:/myproject/uart_lcd/uart_lcd.bdf" { { 72 -24 144 88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.872 ns) + CELL(0.970 ns) 3.111 ns counter2:inst3\|bc 3 REG LCFF_X26_Y10_N17 2 " "Info: 3: + IC(0.872 ns) + CELL(0.970 ns) = 3.111 ns; Loc. = LCFF_X26_Y10_N17; Fanout = 2; REG Node = 'counter2:inst3\|bc'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "1.842 ns" { clk~clkctrl counter2:inst3|bc } "NODE_NAME" } "" } } { "counter2.vhd" "" { Text "E:/myproject/uart_lcd/counter2.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.474 ns) + CELL(0.000 ns) 4.585 ns counter2:inst3\|bc~clkctrl 4 COMB CLKCTRL_G4 5 " "Info: 4: + IC(1.474 ns) + CELL(0.000 ns) = 4.585 ns; Loc. = CLKCTRL_G4; Fanout = 5; COMB Node = 'counter2:inst3\|bc~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "1.474 ns" { counter2:inst3|bc counter2:inst3|bc~clkctrl } "NODE_NAME" } "" } } { "counter2.vhd" "" { Text "E:/myproject/uart_lcd/counter2.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.880 ns) + CELL(0.970 ns) 6.435 ns counter2:inst3\|bclk 5 REG LCFF_X33_Y10_N7 3 " "Info: 5: + IC(0.880 ns) + CELL(0.970 ns) = 6.435 ns; Loc. = LCFF_X33_Y10_N7; Fanout = 3; REG Node = 'counter2:inst3\|bclk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "1.850 ns" { counter2:inst3|bc~clkctrl counter2:inst3|bclk } "NODE_NAME" } "" } } { "counter2.vhd" "" { Text "E:/myproject/uart_lcd/counter2.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.764 ns) + CELL(0.000 ns) 7.199 ns counter2:inst3\|bclk~clkctrl 6 COMB CLKCTRL_G5 28 " "Info: 6: + IC(0.764 ns) + CELL(0.000 ns) = 7.199 ns; Loc. = CLKCTRL_G5; Fanout = 28; COMB Node = 'counter2:inst3\|bclk~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "0.764 ns" { counter2:inst3|bclk counter2:inst3|bclk~clkctrl } "NODE_NAME" } "" } } { "counter2.vhd" "" { Text "E:/myproject/uart_lcd/counter2.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.920 ns) + CELL(0.666 ns) 8.785 ns lcd_driver:inst1\|data\[7\] 7 REG LCFF_X31_Y14_N23 16 " "Info: 7: + IC(0.920 ns) + CELL(0.666 ns) = 8.785 ns; Loc. = LCFF_X31_Y14_N23; Fanout = 16; REG Node = 'lcd_driver:inst1\|data\[7\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "1.586 ns" { counter2:inst3|bclk~clkctrl lcd_driver:inst1|data[7] } "NODE_NAME" } "" } } { "lcd_driver.vhd" "" { Text "E:/myproject/uart_lcd/lcd_driver.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.736 ns ( 42.53 % ) " "Info: Total cell delay = 3.736 ns ( 42.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.049 ns ( 57.47 % ) " "Info: Total interconnect delay = 5.049 ns ( 57.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "8.785 ns" { clk clk~clkctrl counter2:inst3|bc counter2:inst3|bc~clkctrl counter2:inst3|bclk counter2:inst3|bclk~clkctrl lcd_driver:inst1|data[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.785 ns" { clk clk~combout clk~clkctrl counter2:inst3|bc counter2:inst3|bc~clkctrl counter2:inst3|bclk counter2:inst3|bclk~clkctrl lcd_driver:inst1|data[7] } { 0.000ns 0.000ns 0.139ns 0.872ns 1.474ns 0.880ns 0.764ns 0.920ns } { 0.000ns 1.130ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "lcd_driver.vhd" "" { Text "E:/myproject/uart_lcd/lcd_driver.vhd" 45 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.556 ns + Longest register pin " "Info: + Longest register to pin delay is 4.556 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd_driver:inst1\|data\[7\] 1 REG LCFF_X31_Y14_N23 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y14_N23; Fanout = 16; REG Node = 'lcd_driver:inst1\|data\[7\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "" { lcd_driver:inst1|data[7] } "NODE_NAME" } "" } } { "lcd_driver.vhd" "" { Text "E:/myproject/uart_lcd/lcd_driver.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.480 ns) + CELL(3.076 ns) 4.556 ns D\[7\] 2 PIN PIN_138 0 " "Info: 2: + IC(1.480 ns) + CELL(3.076 ns) = 4.556 ns; Loc. = PIN_138; Fanout = 0; PIN Node = 'D\[7\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "4.556 ns" { lcd_driver:inst1|data[7] D[7] } "NODE_NAME" } "" } } { "uart_lcd.bdf" "" { Schematic "E:/myproject/uart_lcd/uart_lcd.bdf" { { 184 848 1024 200 "D\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.076 ns ( 67.52 % ) " "Info: Total cell delay = 3.076 ns ( 67.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.480 ns ( 32.48 % ) " "Info: Total interconnect delay = 1.480 ns ( 32.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "4.556 ns" { lcd_driver:inst1|data[7] D[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.556 ns" { lcd_driver:inst1|data[7] D[7] } { 0.000ns 1.480ns } { 0.000ns 3.076ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "8.785 ns" { clk clk~clkctrl counter2:inst3|bc counter2:inst3|bc~clkctrl counter2:inst3|bclk counter2:inst3|bclk~clkctrl lcd_driver:inst1|data[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.785 ns" { clk clk~combout clk~clkctrl counter2:inst3|bc counter2:inst3|bc~clkctrl counter2:inst3|bclk counter2:inst3|bclk~clkctrl lcd_driver:inst1|data[7] } { 0.000ns 0.000ns 0.139ns 0.872ns 1.474ns 0.880ns 0.764ns 0.920ns } { 0.000ns 1.130ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "4.556 ns" { lcd_driver:inst1|data[7] D[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.556 ns" { lcd_driver:inst1|data[7] D[7] } { 0.000ns 1.480ns } { 0.000ns 3.076ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "reciver:inst\|\\pro2:rbufs\[0\] uart_rxd clk -0.715 ns register " "Info: th for register \"reciver:inst\|\\pro2:rbufs\[0\]\" (data pin = \"uart_rxd\", clock pin = \"clk\") is -0.715 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.924 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 6.924 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN