uart_lcd.tan.qmsg

串口通信的事例FPGA上面可以实现非常实用

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 8 " "Warning: Circuit may not operate. Detected 8 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "reciver:inst\|rbuf\[2\] lcd_driver:inst1\|receive_buffer\[2\] clk 2.152 ns " "Info: Found hold time violation between source  pin or register \"reciver:inst\|rbuf\[2\]\" and destination pin or register \"lcd_driver:inst1\|receive_buffer\[2\]\" for clock \"clk\" (Hold time is 2.152 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.294 ns + Largest " "Info: + Largest clock skew is 4.294 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 11.203 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 11.203 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "" { clk } "NODE_NAME" } "" } } { "uart_lcd.bdf" "" { Schematic "E:/myproject/uart_lcd/uart_lcd.bdf" { { 72 -24 144 88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.269 ns clk~clkctrl 2 COMB CLKCTRL_G2 29 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.269 ns; Loc. = CLKCTRL_G2; Fanout = 29; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "uart_lcd.bdf" "" { Schematic "E:/myproject/uart_lcd/uart_lcd.bdf" { { 72 -24 144 88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.874 ns) + CELL(0.970 ns) 3.113 ns counter1:inst2\|bd_out 3 REG LCFF_X18_Y11_N17 2 " "Info: 3: + IC(0.874 ns) + CELL(0.970 ns) = 3.113 ns; Loc. = LCFF_X18_Y11_N17; Fanout = 2; REG Node = 'counter1:inst2\|bd_out'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "1.844 ns" { clk~clkctrl counter1:inst2|bd_out } "NODE_NAME" } "" } } { "counter1.vhd" "" { Text "E:/myproject/uart_lcd/counter1.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.247 ns) + CELL(0.000 ns) 5.360 ns counter1:inst2\|bd_out~clkctrl 4 COMB CLKCTRL_G7 58 " "Info: 4: + IC(2.247 ns) + CELL(0.000 ns) = 5.360 ns; Loc. = CLKCTRL_G7; Fanout = 58; COMB Node = 'counter1:inst2\|bd_out~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "2.247 ns" { counter1:inst2|bd_out counter1:inst2|bd_out~clkctrl } "NODE_NAME" } "" } } { "counter1.vhd" "" { Text "E:/myproject/uart_lcd/counter1.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.874 ns) + CELL(0.970 ns) 7.204 ns reciver:inst\|r_ready 5 REG LCFF_X18_Y11_N21 2 " "Info: 5: + IC(0.874 ns) + CELL(0.970 ns) = 7.204 ns; Loc. = LCFF_X18_Y11_N21; Fanout = 2; REG Node = 'reciver:inst\|r_ready'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "1.844 ns" { counter1:inst2|bd_out~clkctrl reciver:inst|r_ready } "NODE_NAME" } "" } } { "reciver.vhd" "" { Text "E:/myproject/uart_lcd/reciver.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.427 ns) + CELL(0.000 ns) 9.631 ns reciver:inst\|r_ready~clkctrl 6 COMB CLKCTRL_G6 8 " "Info: 6: + IC(2.427 ns) + CELL(0.000 ns) = 9.631 ns; Loc. = CLKCTRL_G6; Fanout = 8; COMB Node = 'reciver:inst\|r_ready~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "2.427 ns" { reciver:inst|r_ready reciver:inst|r_ready~clkctrl } "NODE_NAME" } "" } } { "reciver.vhd" "" { Text "E:/myproject/uart_lcd/reciver.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.906 ns) + CELL(0.666 ns) 11.203 ns lcd_driver:inst1\|receive_buffer\[2\] 7 REG LCFF_X30_Y12_N9 1 " "Info: 7: + IC(0.906 ns) + CELL(0.666 ns) = 11.203 ns; Loc. = LCFF_X30_Y12_N9; Fanout = 1; REG Node = 'lcd_driver:inst1\|receive_buffer\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "1.572 ns" { reciver:inst|r_ready~clkctrl lcd_driver:inst1|receive_buffer[2] } "NODE_NAME" } "" } } { "lcd_driver.vhd" "" { Text "E:/myproject/uart_lcd/lcd_driver.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.736 ns ( 33.35 % ) " "Info: Total cell delay = 3.736 ns ( 33.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.467 ns ( 66.65 % ) " "Info: Total interconnect delay = 7.467 ns ( 66.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "11.203 ns" { clk clk~clkctrl counter1:inst2|bd_out counter1:inst2|bd_out~clkctrl reciver:inst|r_ready reciver:inst|r_ready~clkctrl lcd_driver:inst1|receive_buffer[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "11.203 ns" { clk clk~combout clk~clkctrl counter1:inst2|bd_out counter1:inst2|bd_out~clkctrl reciver:inst|r_ready reciver:inst|r_ready~clkctrl lcd_driver:inst1|receive_buffer[2] } { 0.000ns 0.000ns 0.139ns 0.874ns 2.247ns 0.874ns 2.427ns 0.906ns } { 0.000ns 1.130ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.909 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 6.909 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "" { clk } "NODE_NAME" } "" } } { "uart_lcd.bdf" "" { Schematic "E:/myproject/uart_lcd/uart_lcd.bdf" { { 72 -24 144 88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.269 ns clk~clkctrl 2 COMB CLKCTRL_G2 29 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.269 ns; Loc. = CLKCTRL_G2; Fanout = 29; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "uart_lcd.bdf" "" { Schematic "E:/myproject/uart_lcd/uart_lcd.bdf" { { 72 -24 144 88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.874 ns) + CELL(0.970 ns) 3.113 ns counter1:inst2\|bd_out 3 REG LCFF_X18_Y11_N17 2 " "Info: 3: + IC(0.874 ns) + CELL(0.970 ns) = 3.113 ns; Loc. = LCFF_X18_Y11_N17; Fanout = 2; REG Node = 'counter1:inst2\|bd_out'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "1.844 ns" { clk~clkctrl counter1:inst2|bd_out } "NODE_NAME" } "" } } { "counter1.vhd" "" { Text "E:/myproject/uart_lcd/counter1.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.247 ns) + CELL(0.000 ns) 5.360 ns counter1:inst2\|bd_out~clkctrl 4 COMB CLKCTRL_G7 58 " "Info: 4: + IC(2.247 ns) + CELL(0.000 ns) = 5.360 ns; Loc. = CLKCTRL_G7; Fanout = 58; COMB Node = 'counter1:inst2\|bd_out~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "2.247 ns" { counter1:inst2|bd_out counter1:inst2|bd_out~clkctrl } "NODE_NAME" } "" } } { "counter1.vhd" "" { Text "E:/myproject/uart_lcd/counter1.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.883 ns) + CELL(0.666 ns) 6.909 ns reciver:inst\|rbuf\[2\] 5 REG LCFF_X18_Y12_N21 1 " "Info: 5: + IC(0.883 ns) + CELL(0.666 ns) = 6.909 ns; Loc. = LCFF_X18_Y12_N21; Fanout = 1; REG Node = 'reciver:inst\|rbuf\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "1.549 ns" { counter1:inst2|bd_out~clkctrl reciver:inst|rbuf[2] } "NODE_NAME" } "" } } { "reciver.vhd" "" { Text "E:/myproject/uart_lcd/reciver.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.766 ns ( 40.03 % ) " "Info: Total cell delay = 2.766 ns ( 40.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.143 ns ( 59.97 % ) " "Info: Total interconnect delay = 4.143 ns ( 59.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "6.909 ns" { clk clk~clkctrl counter1:inst2|bd_out counter1:inst2|bd_out~clkctrl reciver:inst|rbuf[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.909 ns" { clk clk~combout clk~clkctrl counter1:inst2|bd_out counter1:inst2|bd_out~clkctrl reciver:inst|rbuf[2] } { 0.000ns 0.000ns 0.139ns 0.874ns 2.247ns 0.883ns } { 0.000ns 1.130ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "11.203 ns" { clk clk~clkctrl counter1:inst2|bd_out counter1:inst2|bd_out~clkctrl reciver:inst|r_ready reciver:inst|r_ready~clkctrl lcd_driver:inst1|receive_buffer[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "11.203 ns" { clk clk~combout clk~clkctrl counter1:inst2|bd_out counter1:inst2|bd_out~clkctrl reciver:inst|r_ready reciver:inst|r_ready~clkctrl lcd_driver:inst1|receive_buffer[2] } { 0.000ns 0.000ns 0.139ns 0.874ns 2.247ns 0.874ns 2.427ns 0.906ns } { 0.000ns 1.130ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "6.909 ns" { clk clk~clkctrl counter1:inst2|bd_out counter1:inst2|bd_out~clkctrl reciver:inst|rbuf[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.909 ns" { clk clk~combout clk~clkctrl counter1:inst2|bd_out counter1:inst2|bd_out~clkctrl reciver:inst|rbuf[2] } { 0.000ns 0.000ns 0.139ns 0.874ns 2.247ns 0.883ns } { 0.000ns 1.130ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "reciver.vhd" "" { Text "E:/myproject/uart_lcd/reciver.vhd" 31 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.144 ns - Shortest register register " "Info: - Shortest register to register delay is 2.144 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns reciver:inst\|rbuf\[2\] 1 REG LCFF_X18_Y12_N21 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X18_Y12_N21; Fanout = 1; REG Node = 'reciver:inst\|rbuf\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "" { reciver:inst|rbuf[2] } "NODE_NAME" } "" } } { "reciver.vhd" "" { Text "E:/myproject/uart_lcd/reciver.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.830 ns) + CELL(0.206 ns) 2.036 ns lcd_driver:inst1\|receive_buffer\[2\]~feeder 2 COMB LCCOMB_X30_Y12_N8 1 " "Info: 2: + IC(1.830 ns) + CELL(0.206 ns) = 2.036 ns; Loc. = LCCOMB_X30_Y12_N8; Fanout = 1; COMB Node = 'lcd_driver:inst1\|receive_buffer\[2\]~feeder'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "2.036 ns" { reciver:inst|rbuf[2] lcd_driver:inst1|receive_buffer[2]~feeder } "NODE_NAME" } "" } } { "lcd_driver.vhd" "" { Text "E:/myproject/uart_lcd/lcd_driver.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 2.144 ns lcd_driver:inst1\|receive_buffer\[2\] 3 REG LCFF_X30_Y12_N9 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 2.144 ns; Loc. = LCFF_X30_Y12_N9; Fanout = 1; REG Node = 'lcd_driver:inst1\|receive_buffer\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "0.108 ns" { lcd_driver:inst1|receive_buffer[2]~feeder lcd_driver:inst1|receive_buffer[2] } "NODE_NAME" } "" } } { "lcd_driver.vhd" "" { Text "E:/myproject/uart_lcd/lcd_driver.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.314 ns ( 14.65 % ) " "Info: Total cell delay = 0.314 ns ( 14.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.830 ns ( 85.35 % ) " "Info: Total interconnect delay = 1.830 ns ( 85.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "2.144 ns" { reciver:inst|rbuf[2] lcd_driver:inst1|receive_buffer[2]~feeder lcd_driver:inst1|receive_buffer[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.144 ns" { reciver:inst|rbuf[2] lcd_driver:inst1|receive_buffer[2]~feeder lcd_driver:inst1|receive_buffer[2] } { 0.000ns 1.830ns 0.000ns } { 0.000ns 0.206ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "lcd_driver.vhd" "" { Text "E:/myproject/uart_lcd/lcd_driver.vhd" 37 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "11.203 ns" { clk clk~clkctrl counter1:inst2|bd_out counter1:inst2|bd_out~clkctrl reciver:inst|r_ready reciver:inst|r_ready~clkctrl lcd_driver:inst1|receive_buffer[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "11.203 ns" { clk clk~combout clk~clkctrl counter1:inst2|bd_out counter1:inst2|bd_out~clkctrl reciver:inst|r_ready reciver:inst|r_ready~clkctrl lcd_driver:inst1|receive_buffer[2] } { 0.000ns 0.000ns 0.139ns 0.874ns 2.247ns 0.874ns 2.427ns 0.906ns } { 0.000ns 1.130ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "6.909 ns" { clk clk~clkctrl counter1:inst2|bd_out counter1:inst2|bd_out~clkctrl reciver:inst|rbuf[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.909 ns" { clk clk~combout clk~clkctrl counter1:inst2|bd_out counter1:inst2|bd_out~clkctrl reciver:inst|rbuf[2] } { 0.000ns 0.000ns 0.139ns 0.874ns 2.247ns 0.883ns } { 0.000ns 1.130ns 0.000ns 0.970ns 0.000ns 0.666ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "2.144 ns" { reciver:inst|rbuf[2] lcd_driver:inst1|receive_buffer[2]~feeder lcd_driver:inst1|receive_buffer[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.144 ns" { reciver:inst|rbuf[2] lcd_driver:inst1|receive_buffer[2]~feeder lcd_driver:inst1|receive_buffer[2] } { 0.000ns 1.830ns 0.000ns } { 0.000ns 0.206ns 0.108ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "reciver:inst\|\\pro2:rbufs\[0\] reset clk 4.721 ns register " "Info: tsu for register \"reciver:inst\|\\pro2:rbufs\[0\]\" (data pin = \"reset\", clock pin = \"clk\") is 4.721 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.685 ns + Longest pin register " "Info: + Longest pin to register delay is 11.685 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns reset 1 PIN PIN_102 27 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_102; Fanout = 27; PIN Node = 'reset'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "" { reset } "NODE_NAME" } "" } } { "uart_lcd.bdf" "" { Schematic "E:/myproject/uart_lcd/uart_lcd.bdf" { { 256 8 176 272 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.229 ns) + CELL(0.589 ns) 8.812 ns reciver:inst\|Decoder~105 2 COMB LCCOMB_X18_Y11_N2 8 " "Info: 2: + IC(7.229 ns) + CELL(0.589 ns) = 8.812 ns; Loc. = LCCOMB_X18_Y11_N2; Fanout = 8; COMB Node = 'reciver:inst\|Decoder~105'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "7.818 ns" { reset reciver:inst|Decoder~105 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.109 ns) + CELL(0.647 ns) 10.568 ns reciver:inst\|Decoder~113 3 COMB LCCOMB_X17_Y11_N20 1 " "Info: 3: + IC(1.109 ns) + CELL(0.647 ns) = 10.568 ns; Loc. = LCCOMB_X17_Y11_N20; Fanout = 1; COMB Node = 'reciver:inst\|Decoder~113'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "1.756 ns" { reciver:inst|Decoder~105 reciver:inst|Decoder~113 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.615 ns) 11.577 ns reciver:inst\|\\pro2:rbufs\[0\]~8 4 COMB LCCOMB_X17_Y11_N2 1 " "Info: 4: + IC(0.394 ns) + CELL(0.615 ns) = 11.577 ns; Loc. = LCCOMB_X17_Y11_N2; Fanout = 1; COMB Node = 'reciver:inst\|\\pro2:rbufs\[0\]~8'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "1.009 ns" { reciver:inst|Decoder~113 reciver:inst|\pro2:rbufs[0]~8 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 11.685 ns reciver:inst\|\\pro2:rbufs\[0\] 5 REG LCFF_X17_Y11_N3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 11.685 ns; Loc. = LCFF_X17_Y11_N3; Fanout = 2; REG Node = 'reciver:inst\|\\pro2:rbufs\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "0.108 ns" { reciver:inst|\pro2:rbufs[0]~8 reciver:inst|\pro2:rbufs[0] } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.953 ns ( 25.27 % ) " "Info: Total cell delay = 2.953 ns ( 25.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.732 ns ( 74.73 % ) " "Info: Total interconnect delay = 8.732 ns ( 74.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "11.685 ns" { reset reciver:inst|Decoder~105 reciver:inst|Decoder~113 reciver:inst|\pro2:rbufs[0]~8 reciver:inst|\pro2:rbufs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "11.685 ns" { reset reset~combout reciver:inst|Decoder~105 reciver:inst|Decoder~113 reciver:inst|\pro2:rbufs[0]~8 reciver:inst|\pro2:rbufs[0] } { 0.000ns 0.000ns 7.229ns 1.109ns 0.394ns 0.000ns } { 0.000ns 0.994ns 0.589ns 0.647ns 0.615ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.924 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 6.924 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "" { clk } "NODE_NAME" } "" } } { "uart_lcd.bdf" "" { Schematic "E:/myproject/uart_lcd/uart_lcd.bdf" { { 72 -24 144 88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.269 ns clk~clkctrl 2 COMB CLKCTRL_G2 29 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.269 ns; Loc. = CLKCTRL_G2; Fanout = 29; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "uart_lcd.bdf" "" { Schematic "E:/myproject/uart_lcd/uart_lcd.bdf" { { 72 -24 144 88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.874 ns) + CELL(0.970 ns) 3.113 ns counter1:inst2\|bd_out 3 REG LCFF_X18_Y11_N17 2 " "Info: 3: + IC(0.874 ns) + CELL(0.970 ns) = 3.113 ns; Loc. = LCFF_X18_Y11_N17; Fanout = 2; REG Node = 'counter1:inst2\|bd_out'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "1.844 ns" { clk~clkctrl counter1:inst2|bd_out } "NODE_NAME" } "" } } { "counter1.vhd" "" { Text "E:/myproject/uart_lcd/counter1.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.247 ns) + CELL(0.000 ns) 5.360 ns counter1:inst2\|bd_out~clkctrl 4 COMB CLKCTRL_G7 58 " "Info: 4: + IC(2.247 ns) + CELL(0.000 ns) = 5.360 ns; Loc. = CLKCTRL_G7; Fanout = 58; COMB Node = 'counter1:inst2\|bd_out~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "2.247 ns" { counter1:inst2|bd_out counter1:inst2|bd_out~clkctrl } "NODE_NAME" } "" } } { "counter1.vhd" "" { Text "E:/myproject/uart_lcd/counter1.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.898 ns) + CELL(0.666 ns) 6.924 ns reciver:inst\|\\pro2:rbufs\[0\] 5 REG LCFF_X17_Y11_N3 2 " "Info: 5: + IC(0.898 ns) + CELL(0.666 ns) = 6.924 ns; Loc. = LCFF_X17_Y11_N3; Fanout = 2; REG Node = 'reciver:inst\|\\pro2:rbufs\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "1.564 ns" { counter1:inst2|bd_out~clkctrl reciver:inst|\pro2:rbufs[0] } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.766 ns ( 39.95 % ) " "Info: Total cell delay = 2.766 ns ( 39.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.158 ns ( 60.05 % ) " "Info: Total interconnect delay = 4.158 ns ( 60.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "6.924 ns" { clk clk~clkctrl counter1:inst2|bd_out counter1:inst2|bd_out~clkctrl reciver:inst|\pro2:rbufs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.924 ns" { clk clk~combout clk~clkctrl counter1:inst2|bd_out counter1:inst2|bd_out~clkctrl reciver:inst|\pro2:rbufs[0] } { 0.000ns 0.000ns 0.139ns 0.874ns 2.247ns 0.898ns } { 0.000ns 1.130ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "11.685 ns" { reset reciver:inst|Decoder~105 reciver:inst|Decoder~113 reciver:inst|\pro2:rbufs[0]~8 reciver:inst|\pro2:rbufs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "11.685 ns" { reset reset~combout reciver:inst|Decoder~105 reciver:inst|Decoder~113 reciver:inst|\pro2:rbufs[0]~8 reciver:inst|\pro2:rbufs[0] } { 0.000ns 0.000ns 7.229ns 1.109ns 0.394ns 0.000ns } { 0.000ns 0.994ns 0.589ns 0.647ns 0.615ns 0.108ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "6.924 ns" { clk clk~clkctrl counter1:inst2|bd_out counter1:inst2|bd_out~clkctrl reciver:inst|\pro2:rbufs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.924 ns" { clk clk~combout clk~clkctrl counter1:inst2|bd_out counter1:inst2|bd_out~clkctrl reciver:inst|\pro2:rbufs[0] } { 0.000ns 0.000ns 0.139ns 0.874ns 2.247ns 0.898ns } { 0.000ns 1.130ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}