uart_lcd.tan.qmsg

串口通信的事例FPGA上面可以实现非常实用

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "uart_lcd.bdf" "" { Schematic "E:/myproject/uart_lcd/uart_lcd.bdf" { { 72 -24 144 88 "clk" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "counter1:inst2\|bd_out " "Info: Detected ripple clock \"counter1:inst2\|bd_out\" as buffer" {  } { { "counter1.vhd" "" { Text "E:/myproject/uart_lcd/counter1.vhd" 8 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "counter1:inst2\|bd_out" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "reciver:inst\|r_ready " "Info: Detected ripple clock \"reciver:inst\|r_ready\" as buffer" {  } { { "reciver.vhd" "" { Text "E:/myproject/uart_lcd/reciver.vhd" 9 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "reciver:inst\|r_ready" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "counter2:inst3\|bc " "Info: Detected ripple clock \"counter2:inst3\|bc\" as buffer" {  } { { "counter2.vhd" "" { Text "E:/myproject/uart_lcd/counter2.vhd" 12 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "counter2:inst3\|bc" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "counter2:inst3\|bclk " "Info: Detected ripple clock \"counter2:inst3\|bclk\" as buffer" {  } { { "counter2.vhd" "" { Text "E:/myproject/uart_lcd/counter2.vhd" 7 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "counter2:inst3\|bclk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register reciver:inst\|\\pro2:rcnt\[5\] register reciver:inst\|state.r_sample 190.88 MHz 5.239 ns Internal " "Info: Clock \"clk\" has Internal fmax of 190.88 MHz between source register \"reciver:inst\|\\pro2:rcnt\[5\]\" and destination register \"reciver:inst\|state.r_sample\" (period= 5.239 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.994 ns + Longest register register " "Info: + Longest register to register delay is 4.994 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns reciver:inst\|\\pro2:rcnt\[5\] 1 REG LCFF_X17_Y10_N11 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X17_Y10_N11; Fanout = 3; REG Node = 'reciver:inst\|\\pro2:rcnt\[5\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "" { reciver:inst|\pro2:rcnt[5] } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.397 ns) + CELL(0.529 ns) 1.926 ns rtl~588 2 COMB LCCOMB_X17_Y8_N12 1 " "Info: 2: + IC(1.397 ns) + CELL(0.529 ns) = 1.926 ns; Loc. = LCCOMB_X17_Y8_N12; Fanout = 1; COMB Node = 'rtl~588'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "1.926 ns" { reciver:inst|\pro2:rcnt[5] rtl~588 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.355 ns) + CELL(0.589 ns) 3.870 ns rtl~591 3 COMB LCCOMB_X17_Y11_N10 2 " "Info: 3: + IC(1.355 ns) + CELL(0.589 ns) = 3.870 ns; Loc. = LCCOMB_X17_Y11_N10; Fanout = 2; COMB Node = 'rtl~591'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "1.944 ns" { rtl~588 rtl~591 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.401 ns) + CELL(0.615 ns) 4.886 ns reciver:inst\|state~91 4 COMB LCCOMB_X17_Y11_N16 1 " "Info: 4: + IC(0.401 ns) + CELL(0.615 ns) = 4.886 ns; Loc. = LCCOMB_X17_Y11_N16; Fanout = 1; COMB Node = 'reciver:inst\|state~91'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "1.016 ns" { rtl~591 reciver:inst|state~91 } "NODE_NAME" } "" } } { "reciver.vhd" "" { Text "E:/myproject/uart_lcd/reciver.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 4.994 ns reciver:inst\|state.r_sample 5 REG LCFF_X17_Y11_N17 35 " "Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 4.994 ns; Loc. = LCFF_X17_Y11_N17; Fanout = 35; REG Node = 'reciver:inst\|state.r_sample'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "0.108 ns" { reciver:inst|state~91 reciver:inst|state.r_sample } "NODE_NAME" } "" } } { "reciver.vhd" "" { Text "E:/myproject/uart_lcd/reciver.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.841 ns ( 36.86 % ) " "Info: Total cell delay = 1.841 ns ( 36.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.153 ns ( 63.14 % ) " "Info: Total interconnect delay = 3.153 ns ( 63.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "4.994 ns" { reciver:inst|\pro2:rcnt[5] rtl~588 rtl~591 reciver:inst|state~91 reciver:inst|state.r_sample } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.994 ns" { reciver:inst|\pro2:rcnt[5] rtl~588 rtl~591 reciver:inst|state~91 reciver:inst|state.r_sample } { 0.000ns 1.397ns 1.355ns 0.401ns 0.000ns } { 0.000ns 0.529ns 0.589ns 0.615ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.019 ns - Smallest " "Info: - Smallest clock skew is 0.019 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.924 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 6.924 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "" { clk } "NODE_NAME" } "" } } { "uart_lcd.bdf" "" { Schematic "E:/myproject/uart_lcd/uart_lcd.bdf" { { 72 -24 144 88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.269 ns clk~clkctrl 2 COMB CLKCTRL_G2 29 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.269 ns; Loc. = CLKCTRL_G2; Fanout = 29; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "uart_lcd.bdf" "" { Schematic "E:/myproject/uart_lcd/uart_lcd.bdf" { { 72 -24 144 88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.874 ns) + CELL(0.970 ns) 3.113 ns counter1:inst2\|bd_out 3 REG LCFF_X18_Y11_N17 2 " "Info: 3: + IC(0.874 ns) + CELL(0.970 ns) = 3.113 ns; Loc. = LCFF_X18_Y11_N17; Fanout = 2; REG Node = 'counter1:inst2\|bd_out'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "1.844 ns" { clk~clkctrl counter1:inst2|bd_out } "NODE_NAME" } "" } } { "counter1.vhd" "" { Text "E:/myproject/uart_lcd/counter1.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.247 ns) + CELL(0.000 ns) 5.360 ns counter1:inst2\|bd_out~clkctrl 4 COMB CLKCTRL_G7 58 " "Info: 4: + IC(2.247 ns) + CELL(0.000 ns) = 5.360 ns; Loc. = CLKCTRL_G7; Fanout = 58; COMB Node = 'counter1:inst2\|bd_out~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "2.247 ns" { counter1:inst2|bd_out counter1:inst2|bd_out~clkctrl } "NODE_NAME" } "" } } { "counter1.vhd" "" { Text "E:/myproject/uart_lcd/counter1.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.898 ns) + CELL(0.666 ns) 6.924 ns reciver:inst\|state.r_sample 5 REG LCFF_X17_Y11_N17 35 " "Info: 5: + IC(0.898 ns) + CELL(0.666 ns) = 6.924 ns; Loc. = LCFF_X17_Y11_N17; Fanout = 35; REG Node = 'reciver:inst\|state.r_sample'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "1.564 ns" { counter1:inst2|bd_out~clkctrl reciver:inst|state.r_sample } "NODE_NAME" } "" } } { "reciver.vhd" "" { Text "E:/myproject/uart_lcd/reciver.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.766 ns ( 39.95 % ) " "Info: Total cell delay = 2.766 ns ( 39.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.158 ns ( 60.05 % ) " "Info: Total interconnect delay = 4.158 ns ( 60.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "6.924 ns" { clk clk~clkctrl counter1:inst2|bd_out counter1:inst2|bd_out~clkctrl reciver:inst|state.r_sample } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.924 ns" { clk clk~combout clk~clkctrl counter1:inst2|bd_out counter1:inst2|bd_out~clkctrl reciver:inst|state.r_sample } { 0.000ns 0.000ns 0.139ns 0.874ns 2.247ns 0.898ns } { 0.000ns 1.130ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.905 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 6.905 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "" { clk } "NODE_NAME" } "" } } { "uart_lcd.bdf" "" { Schematic "E:/myproject/uart_lcd/uart_lcd.bdf" { { 72 -24 144 88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.269 ns clk~clkctrl 2 COMB CLKCTRL_G2 29 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.269 ns; Loc. = CLKCTRL_G2; Fanout = 29; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "uart_lcd.bdf" "" { Schematic "E:/myproject/uart_lcd/uart_lcd.bdf" { { 72 -24 144 88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.874 ns) + CELL(0.970 ns) 3.113 ns counter1:inst2\|bd_out 3 REG LCFF_X18_Y11_N17 2 " "Info: 3: + IC(0.874 ns) + CELL(0.970 ns) = 3.113 ns; Loc. = LCFF_X18_Y11_N17; Fanout = 2; REG Node = 'counter1:inst2\|bd_out'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "1.844 ns" { clk~clkctrl counter1:inst2|bd_out } "NODE_NAME" } "" } } { "counter1.vhd" "" { Text "E:/myproject/uart_lcd/counter1.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.247 ns) + CELL(0.000 ns) 5.360 ns counter1:inst2\|bd_out~clkctrl 4 COMB CLKCTRL_G7 58 " "Info: 4: + IC(2.247 ns) + CELL(0.000 ns) = 5.360 ns; Loc. = CLKCTRL_G7; Fanout = 58; COMB Node = 'counter1:inst2\|bd_out~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "2.247 ns" { counter1:inst2|bd_out counter1:inst2|bd_out~clkctrl } "NODE_NAME" } "" } } { "counter1.vhd" "" { Text "E:/myproject/uart_lcd/counter1.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.879 ns) + CELL(0.666 ns) 6.905 ns reciver:inst\|\\pro2:rcnt\[5\] 5 REG LCFF_X17_Y10_N11 3 " "Info: 5: + IC(0.879 ns) + CELL(0.666 ns) = 6.905 ns; Loc. = LCFF_X17_Y10_N11; Fanout = 3; REG Node = 'reciver:inst\|\\pro2:rcnt\[5\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "1.545 ns" { counter1:inst2|bd_out~clkctrl reciver:inst|\pro2:rcnt[5] } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.766 ns ( 40.06 % ) " "Info: Total cell delay = 2.766 ns ( 40.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.139 ns ( 59.94 % ) " "Info: Total interconnect delay = 4.139 ns ( 59.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "6.905 ns" { clk clk~clkctrl counter1:inst2|bd_out counter1:inst2|bd_out~clkctrl reciver:inst|\pro2:rcnt[5] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.905 ns" { clk clk~combout clk~clkctrl counter1:inst2|bd_out counter1:inst2|bd_out~clkctrl reciver:inst|\pro2:rcnt[5] } { 0.000ns 0.000ns 0.139ns 0.874ns 2.247ns 0.879ns } { 0.000ns 1.130ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "6.924 ns" { clk clk~clkctrl counter1:inst2|bd_out counter1:inst2|bd_out~clkctrl reciver:inst|state.r_sample } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.924 ns" { clk clk~combout clk~clkctrl counter1:inst2|bd_out counter1:inst2|bd_out~clkctrl reciver:inst|state.r_sample } { 0.000ns 0.000ns 0.139ns 0.874ns 2.247ns 0.898ns } { 0.000ns 1.130ns 0.000ns 0.970ns 0.000ns 0.666ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "6.905 ns" { clk clk~clkctrl counter1:inst2|bd_out counter1:inst2|bd_out~clkctrl reciver:inst|\pro2:rcnt[5] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.905 ns" { clk clk~combout clk~clkctrl counter1:inst2|bd_out counter1:inst2|bd_out~clkctrl reciver:inst|\pro2:rcnt[5] } { 0.000ns 0.000ns 0.139ns 0.874ns 2.247ns 0.879ns } { 0.000ns 1.130ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "reciver.vhd" "" { Text "E:/myproject/uart_lcd/reciver.vhd" 31 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "4.994 ns" { reciver:inst|\pro2:rcnt[5] rtl~588 rtl~591 reciver:inst|state~91 reciver:inst|state.r_sample } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.994 ns" { reciver:inst|\pro2:rcnt[5] rtl~588 rtl~591 reciver:inst|state~91 reciver:inst|state.r_sample } { 0.000ns 1.397ns 1.355ns 0.401ns 0.000ns } { 0.000ns 0.529ns 0.589ns 0.615ns 0.108ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "6.924 ns" { clk clk~clkctrl counter1:inst2|bd_out counter1:inst2|bd_out~clkctrl reciver:inst|state.r_sample } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.924 ns" { clk clk~combout clk~clkctrl counter1:inst2|bd_out counter1:inst2|bd_out~clkctrl reciver:inst|state.r_sample } { 0.000ns 0.000ns 0.139ns 0.874ns 2.247ns 0.898ns } { 0.000ns 1.130ns 0.000ns 0.970ns 0.000ns 0.666ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "uart_lcd" "UNKNOWN" "V1" "E:/myproject/uart_lcd/db/uart_lcd.quartus_db" { Floorplan "E:/myproject/uart_lcd/" "" "6.905 ns" { clk clk~clkctrl counter1:inst2|bd_out counter1:inst2|bd_out~clkctrl reciver:inst|\pro2:rcnt[5] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.905 ns" { clk clk~combout clk~clkctrl counter1:inst2|bd_out counter1:inst2|bd_out~clkctrl reciver:inst|\pro2:rcnt[5] } { 0.000ns 0.000ns 0.139ns 0.874ns 2.247ns 0.879ns } { 0.000ns 1.130ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}