trafficlight.v

fpga的交通灯试验程序 可成功实现功能齐全

module trafficlight(
clk,
rst,
en,
lamp_a,
lamp_b,
count_a,
count_b
);

//input
input clk;
input rst;
input en;
//output
output[3:0] lamp_a;
output[3:0] lamp_b;
output[7:0] count_a;
output[7:0] count_b;

// Reg/Wire Description
wire clk;
wire rst;
wire en;
reg[3:0] lamp_a;
reg[3:0] lamp_b;
reg[7:0] count_a;
reg[7:0] count_b;

reg[7:0] red_num_a;
reg[7:0] yellow_num_a;
reg[7:0] left_num_a;
reg[7:0] green_num_a;

reg[7:0] red_num_b;
reg[7:0] yellow_num_b;
reg[7:0] left_num_b;
reg[7:0] green_num_b;
reg[7:0] state;
reg change;

always@(rst)
if(!rst)
begin
	red_num_a<=8'd55;
	yellow_num_a<=8'd5;
	left_num_a<=8'd15;
	green_num_a<=8'd40;
	
	red_num_b<=8'd65;
	yellow_num_b=8'd5;
	left_num_b<=8'd15;
	green_num_b<=8'd30;
end

always@(posedge clk)
if(!rst)
begin
	state<=0;
	change<=0;
end

always@(posedge clk)
if(rst&&!change)
begin
		change<=1;
		case(state)
			8'h01:state<=8'h02;
			8'h02:state<=8'h04;
			8'h04:state<=8'h08;
			8'h08:state<=8'h10;
			8'h10:state<=8'h20;
			8'h20:state<=8'h40;
			8'h40:state<=8'h80;
			8'h80:state<=8'h01;
		default:state<=8'h01;
		endcase
end

always@(posedge clk or state)
if(rst)
begin
	case(state)
		8'h01:count_a<=green_num_a;
		8'h02:count_a<=yellow_num_a;
		8'h04:count_a<=left_num_a;
		8'h08:count_a<=yellow_num_a;
		8'h10:count_a<=red_num_a;
		default:count_a<=count_a;
end

always@(posedge clk)
if(rst&&change)
begin
	if(count_a>1)
		count_a<=count_a-1;
	if(count_a==2)
		change<=0;
end

endmodule