_primary.vhd

基于Fusion系列AFS600的FPGA的51核

library verilog;
use verilog.vl_types.all;
entity XYXX0005 is
    port(
        MXXXXXXXXXXXXXXYXLXXXXXX: in     vl_logic;
        MXXXXXXXXXXXXXXYXLXXXXXX0: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXX: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXXX0: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXXX1: out    vl_logic;
        MXXXXXXXXXXXXXXXXXMXXXXXXXXXX: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXXX2: out    vl_logic;
        MXXXXXXXXXXXXXXXXXMXXXXXXXXXX0: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXXX3: out    vl_logic;
        XXXXXXXXXXXXXX  : in     vl_logic;
        MXXXXXXXXXXXXXXXXXXFXWXXX: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXXFXWXXX: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXXFXWXXX0: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXFXWXXX1: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXFXXXXXXX: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXFXWXXX0: out    vl_logic;
        MXXXXXXXXXXXXXXXXXMXXXXXXXXXFXWXXXXX: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXFXWXXXXX: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXFXWXXX2: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXFXWXXX1: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXMXXVXXXXXXX: out    vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXMXXVXXXXXXX0: out    vl_logic;
        MXXXXXXXXXXXXXXXXXX: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXMXXVXXXXX: out    vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXMXXVXXXXX0: out    vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXMXXVXXXXX1: out    vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXMXXVXXXXX2: out    vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXMXXVXXXXX3: out    vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXMXXVXXXXX4: out    vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXMXXVXXXXX5: out    vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXMXXVXXXXX6: out    vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXMXXVXXXXX7: out    vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXMXXVXXXXX8: out    vl_logic;
        XFXXXXXXXXXX    : in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXX: in     vl_logic;
        MXXXXXXXXXXXXXXXX: out    vl_logic;
        XXXX            : in     vl_logic;
        MXXXXXXXXXXXXXXXX0: out    vl_logic;
        XXXX0           : in     vl_logic;
        MXXXXXXXXXXXXXXXX1: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXXX4: in     vl_logic;
        MXXXXXXXXXXXXXXXX2: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXXX5: in     vl_logic;
        MXXXXXXXXXXXXXXYXLXXXXXX1: in     vl_logic;
        MXXXXXXXXXXXXXXYXLXXXX: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXX: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXX0: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXX1: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXX2: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXX3: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXX4: in     vl_logic;
        XFXXXXXXXXXXX   : in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXXXX: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXMXXX: out    vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXMXXX0: out    vl_logic;
        MXXXXXXXXXXXXXXYXLXXXX0: in     vl_logic;
        MXXXXXXXXXXXXXXYXLXXXX1: in     vl_logic;
        MXXXXXXXXXXXXXXXXXX0: out    vl_logic;
        MXXXXXXXXXXXXXXLXXXVXX: in     vl_logic;
        MXXXXXXXXXXXXXXFX: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXXX6: in     vl_logic;
        MXXXXXXXXXXXXXXFX0: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXXX7: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXX: in     vl_logic;
        XFXXXXXXXXXXX0  : in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXX5: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXX6: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXX7: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXX8: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXX9: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXX10: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXX8: in     vl_logic;
        MXXXXXXXXXXXXXXXXXPXWXXXXWXXXXX: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXX0: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXFXWXXX3: in     vl_logic;
        MXXXXXXXXXXXXXXXXXPXWXXXXWXXX: in     vl_logic;
        MXXXXXXXXXXXXXXXXXX1: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXFXWXXX4: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXX1: in     vl_logic;
        XFXWX           : in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXX2: in     vl_logic;
        ramaddr         : in     vl_logic_vector(3 downto 0);
        MXXXXXXXXXXXXXXXXVXX: out    vl_logic;
        XLXPXX          : in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXX: in     vl_logic;
        XX              : in     vl_logic;
        XX0             : in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXXXX: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXX0: in     vl_logic;
        XFXXXXXX        : in     vl_logic_vector(7 downto 1);
        MXXXXXXXXXXXXXXFXXXXXXXXXXXXXXX: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXX1: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXX2: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXX3: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXX4: in     vl_logic
    );
end XYXX0005;