_primary.vhd

基于Fusion系列AFS600的FPGA的51核

library verilog;
use verilog.vl_types.all;
entity XYXX0006 is
    port(
        MXXXXXXXXXXXXXXFXXXXXXXXXXXX: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXXX0: in     vl_logic;
        MXXXXXXXXXXXXXXXXXPXWXXXXWXXXXX: out    vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXXXXXX: in     vl_logic;
        XLXPXX          : in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXX: in     vl_logic;
        MXXXXXXXXXXXXXXXXPXXXXXXXXXX: out    vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXX: in     vl_logic;
        XFXXXXXXXXXXX   : in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXLXXX: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXXLXXX0: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXXLXXX1: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXXX0: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXXLX: out    vl_logic;
        MXXXXXXXXXXXXXXXXVXXXXXX: out    vl_logic;
        MXXXXXXXXXXXXXXXXVXXXXXX0: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXX: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXX: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXXXX0: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXXX1: in     vl_logic;
        MXXXXXXXXXXXXXXYXXXX: in     vl_logic;
        MXXXXXXXXXXXXXXYXX: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXFXXXXX: in     vl_logic;
        MXXXXXXXXXXXXXXXXPXXXXXXXX: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXXXX1: out    vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXVXXXXX: out    vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXVXXXXXXX: out    vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXVXXXXX0: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXFXXXXX: out    vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXVXXXXX1: out    vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXVXXXXX2: out    vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXVXXXXX3: out    vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXVXXXXX4: out    vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXVXXXXX5: out    vl_logic;
        MXXXXXXXXXXXXXXXXXX: out    vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXVXXXXXXX0: out    vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXVXXXXXXX1: out    vl_logic;
        MXXXXXXXXXXXXXXXXXX0: out    vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXVXXXXXXX2: out    vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXVXXXXXXX3: out    vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXVXXXXXXX4: out    vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXVXXXXXXX5: out    vl_logic;
        MXXXXXXXXXXXXXXXXPXXXXXXXX0: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXX0: in     vl_logic;
        MXXXXXXXXXXXXXXXXPXXXXXXXX1: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXX1: in     vl_logic;
        MXXXXXXXXXXXXXXXXVXXXXXX1: out    vl_logic;
        MXXXXXXXXXXXXXXXXVXXXXXX2: out    vl_logic;
        MXXXXXXXXXXXXXXXXVXXXXXX3: out    vl_logic;
        MXXXXXXXXXXXXXXXXPXXXXXXXX2: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXXXX2: out    vl_logic;
        MXXXXXXXXXXXXXXFX: in     vl_logic;
        MXXXXXXXXXXXXXXFX0: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXXXXXXX: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXX2: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXXXXVXXXXXXXXXX: in     vl_logic;
        MXXXXXXXXXXXXXXXL: out    vl_logic;
        MXXXXXXXXXXXXXXXX: in     vl_logic;
        MXXXXXXXXXXXXXXXX0: in     vl_logic;
        MXXXXXXXXXXXXXXXXXX1: out    vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXX: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXXX1: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXX0: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXMXXX: out    vl_logic;
        MXXXXXXXXXXXXXXXXXX2: out    vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXX1: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXX2: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXX3: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXX4: in     vl_logic;
        XFXWX           : in     vl_logic;
        ramaddr         : in     vl_logic_vector(2 downto 1);
        MXXXXXXXXXXXXXXXXXPXWXXXXWXXX: out    vl_logic;
        MXXXXXXXXXXXXXXXX1: in     vl_logic;
        MXXXXXXXXXXXXXXXX2: in     vl_logic;
        XXXXX           : in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXX3: in     vl_logic;
        XXXXX0          : in     vl_logic;
        XXXX            : in     vl_logic;
        XXXX0           : in     vl_logic;
        XXXX1           : in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXXXX: in     vl_logic;
        XXXX2           : in     vl_logic;
        XXXX3           : in     vl_logic;
        XXXX4           : in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXX2: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXXX3: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXXXX4: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXX4: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXXX5: out    vl_logic;
        MXXXXXXXXXXXXXXXXXFXXXHXXX: in     vl_logic;
        MXXXXXXXXXXXXXXXXXFXXXHX: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXX0: in     vl_logic;
        XFXXXXXX        : in     vl_logic_vector(7 downto 0);
        XFXXXXXXXXXXX0  : in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXX1: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXX2: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXX3: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXX5: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXX6: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXX7: in     vl_logic
    );
end XYXX0006;