_primary.vhd

来自「基于Fusion系列AFS600的FPGA的51核」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity pll10m is
    port(
        POWERDOWN       : in     vl_logic;
        CLKA            : in     vl_logic;
        LOCK            : out    vl_logic;
        GLA             : out    vl_logic;
        OADIVRST        : in     vl_logic
    );
end pll10m;