_primary.vhd

来自「基于Fusion系列AFS600的FPGA的51核」· VHDL 代码 · 共 64 行

library verilog;
use verilog.vl_types.all;
entity XYXX0004 is
    port(
        XLXPXX          : in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXXXX: in     vl_logic;
        MXXXXXXXXXXXXXXFXWXXX: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXX: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXFXXXXXXXXX: in     vl_logic;
        MXXXXXXXXXXXXXXXX: out    vl_logic;
        MXXXXXXXXXXXXXXXX0: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXXXX: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXXXXXXX: in     vl_logic;
        MXXXXXXXXXXXXXXLXXXXXXXXXX: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXX: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXXX: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXX0: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXX1: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXX: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXX: in     vl_logic;
        XFXXXXXXXXXXX   : in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXX2: in     vl_logic;
        XFXXXXXXXXXXX0  : in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXX3: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXX4: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXX5: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXX6: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXX7: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXX8: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXX9: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXXX0: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXX: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXX0: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXX1: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXX2: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXX3: out    vl_logic;
        XFXWX           : in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXX0: in     vl_logic;
        MXXXXXXXXXXXXXXLXXXVXX: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXX4: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXX5: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXX6: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXXXXXXXLXX: in     vl_logic;
        MXXXXXXXXXXXXXXLXXXVX: in     vl_logic;
        MXXXXXXXXXXXXXXMXX: in     vl_logic;
        MXXXXXXXXXXXXXXLXXXVX0: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXX0: in     vl_logic;
        MXXXXXXXXXXXXXXXXVXX: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXX0: in     vl_logic;
        XXXXX           : in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXXXX0: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXX1: in     vl_logic;
        XXXXX0          : out    vl_logic;
        MXXXXXXXXXXXXXXXXXXXXX2: in     vl_logic;
        XXXX            : out    vl_logic;
        MXXXXXXXXXXXXXXXXXXXXX3: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXX4: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXX5: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXX6: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXX7: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXX8: in     vl_logic
    );
end XYXX0004;