_primary.vhd

来自「基于Fusion系列AFS600的FPGA的51核」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity Core8051_ROM_Ctr is
    port(
        clk_ctr         : in     vl_logic;
        rst             : in     vl_logic;
        BUSY            : in     vl_logic;
        mempsacki       : out    vl_logic
    );
end Core8051_ROM_Ctr;