_primary.vhd

来自「基于Fusion系列AFS600的FPGA的51核」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity RAM256X8 is
    port(
        WD              : in     vl_logic_vector(7 downto 0);
        RD              : out    vl_logic_vector(7 downto 0);
        WEN             : in     vl_logic;
        REN             : in     vl_logic;
        WADDR           : in     vl_logic_vector(7 downto 0);
        RADDR           : in     vl_logic_vector(7 downto 0);
        WCLK            : in     vl_logic;
        RCLK            : in     vl_logic
    );
end RAM256X8;