_primary.vhd

来自「基于Fusion系列AFS600的FPGA的51核」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity flashmem is
    port(
        memaddr         : in     vl_logic_vector(15 downto 0);
        memdatai        : out    vl_logic_vector(7 downto 0);
        reset_c_i       : in     vl_logic;
        mempsrd         : in     vl_logic;
        mcuclk_i_0      : in     vl_logic;
        flashmem_GND    : in     vl_logic;
        BUSY            : out    vl_logic
    );
end flashmem;