_primary.vhd

来自「基于Fusion系列AFS600的FPGA的51核」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity USER_CORE8051 is
    port(
        reset           : in     vl_logic;
        clk48m          : in     vl_logic;
        port0o          : out    vl_logic_vector(7 downto 0);
        port1o          : out    vl_logic_vector(7 downto 0)
    );
end USER_CORE8051;