_primary.vhd

来自「基于Fusion系列AFS600的FPGA的51核」· VHDL 代码 · 共 13 行

library verilog;
use verilog.vl_types.all;
entity pll10m is
    port(
        pll10m_VCC      : in     vl_logic;
        pll10m_GND      : in     vl_logic;
        mcuclk_i        : out    vl_logic;
        clk48m_c        : in     vl_logic;
        mcuclk          : in     vl_logic;
        mcuclk_i_0      : out    vl_logic
    );
end pll10m;