_primary.vhd

来自「基于Fusion系列AFS600的FPGA的51核」· VHDL 代码 · 共 54 行

library verilog;
use verilog.vl_types.all;
entity XYXX0004 is
    port(
        MXXXXXXXXXXXXXXXXXXXXXXX24: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXX9: in     vl_logic;
        MXXXXXXXXXXXXXXFXWXXX: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXX24: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXXXXXXX1: in     vl_logic;
        MXXXXXXXXXXXXXXLXXXXXXXXXX2: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXX6: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXX24: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXX121: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXX125: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXX122: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXX118: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXX124: out    vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXX: in     vl_logic;
        XFXXXXXXXXXXX   : in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXX10: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXX0: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXX: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXX9: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXXX8: in     vl_logic;
        MXXXXXXXXXXXXXXXXXMXFXXXXLXXFXWXXXXXX: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXFXXXXXXXXX: in     vl_logic;
        MXXXXXXXXXXXXXXFXXXXXXXXXX6: in     vl_logic;
        MXXXXXXXXXXXXXXLXXXVXX: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXX123: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXX120: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXX119: out    vl_logic;
        MXXXXXXXXXXXXXXLXXXVX: in     vl_logic;
        MXXXXXXXXXXXXXXLXXXVX0: in     vl_logic;
        MXXXXXXXXXXXXXXMXX: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXX12: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXXX: in     vl_logic;
        MXXXXXXXXXXXXXXXXVXX: in     vl_logic;
        XYXX0004_GND    : in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXX57: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXXXX25: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXX58: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXX59: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXX60: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXX61: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXX62: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXX63: in     vl_logic;
        MXXXXXXXXXXXXXXXX5: out    vl_logic;
        MXXXXXXXXXXXXXXXX4: out    vl_logic;
        MXXXXXXXXXXXXXXXXXXXXX64: in     vl_logic;
        MXXXXXXXXXXXXXXXXXXXXX65: in     vl_logic;
        mcuclk          : in     vl_logic
    );
end XYXX0004;