_primary.vhd

基于Fusion系列AFS600的FPGA的51核

library verilog;
use verilog.vl_types.all;
entity Core8051_ROM_Ctr is
    port(
        reset_c         : in     vl_logic;
        clk48m_c        : in     vl_logic;
        BUSY            : in     vl_logic;
        mempsacki       : out    vl_logic
    );
end Core8051_ROM_Ctr;