_primary.vhd

基于Fusion系列AFS600的FPGA的51核

library verilog;
use verilog.vl_types.all;
entity CORE8051 is
    port(
        memaddr         : out    vl_logic_vector(15 downto 0);
        ramdatai        : in     vl_logic_vector(7 downto 0);
        ramdatao        : out    vl_logic_vector(7 downto 0);
        memdatai        : in     vl_logic_vector(7 downto 0);
        ramaddr         : out    vl_logic_vector(7 downto 0);
        port1o_c        : out    vl_logic_vector(7 downto 0);
        port0o_c        : out    vl_logic_vector(7 downto 0);
        ramoe           : out    vl_logic;
        ramwe           : out    vl_logic;
        mempsrd         : out    vl_logic;
        mempsacki       : in     vl_logic;
        CORE8051_GND    : in     vl_logic;
        reset_c         : in     vl_logic;
        mcuclk          : in     vl_logic
    );
end CORE8051;