_primary.vhd

来自「基于Fusion系列AFS600的FPGA的51核」· VHDL 代码 · 共 16 行

library verilog;
use verilog.vl_types.all;
entity RAM256X8 is
    port(
        ramdatao        : in     vl_logic_vector(7 downto 0);
        ramaddr         : in     vl_logic_vector(7 downto 0);
        ramdatai        : out    vl_logic_vector(7 downto 0);
        ramoe           : in     vl_logic;
        RAM256X8_VCC    : in     vl_logic;
        mcuclk_i_0      : in     vl_logic;
        mcuclk          : in     vl_logic;
        RAM256X8_GND    : in     vl_logic;
        ramwe           : in     vl_logic
    );
end RAM256X8;