📄 m32rx.s
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# Test new instructionsbranchpoint: .text .global bclbcl: bcl branchpoint .text .global bnclbncl: bncl branchpoint .text .global cmpzcmpz: cmpz fp .text .global cmpeqcmpeq: cmpeq fp, fp .text .global maclh1maclh1: maclh1 fp, fp .text .global macsl0msblo: msblo fp, fp .text .global mulwu1mulwu1: mulwu1 fp, fp .text .global macwu1macwu1: macwu1 fp, fp .text .global saddsadd: sadd .text .global satbsatb: satb fp, fp .text .global mulhimulhi: mulhi fp, fp, a1 .text .global mullomullo: mullo fp, fp, a0 .text .global divhdivh: divh fp, fp .text .global machimachi: machi fp, fp, a1 .text .global maclomaclo: maclo fp, fp, a0 .text .global mvfachimvfachi: mvfachi fp, a1 .text .global mvfacmimvfacmi: mvfacmi fp, a1 .text .global mvfaclomvfaclo: mvfaclo fp, a1 .text .global mvtachimvtachi: mvtachi fp, a1 .text .global mvtaclomvtaclo: mvtaclo fp, a0 .text .global racrac: rac a1 .text .global rac_dsrac_ds: rac a1, a0 .text .global rac_dsirac_dsi: rac a0, a1, #1 .text .global rachrach: rach a1 .text .global rach_dsrach_ds: rach a0, a1 .text .global rach_dsirach_dsi: rach a1, a0, #2 # Test explicitly parallel and implicitly parallel instructions# Including apparent instruction sequence reordering. .text .global bc__addbc__add: bc bcl || add fp, fp# Use bc.s here as bc is relaxable and thus a nop will be emitted. bc.s bcl add fp, fp .text .global bcl__addibcl__addi: bcl bcl || addi fp, #77 addi fp, #77# Use bcl.s here as bcl is relaxable and thus the parallelization won't happen. bcl.s bcl .text .global bl__addvbl__addv: bl bcl || addv fp, fp addv fp, fp# Use bl.s here as bl is relaxable and thus the parallelization won't happen. bl.s bcl .text .global bnc__addxbnc__addx: bnc bcl || addx fp, fp# Use bnc.s here as bnc is relaxable and thus the parallelization attempt won't# happen. Things still won't be parallelized, but we want this test to try. bnc.s bcl addx fp, fp .text .global bncl__andbncl__and: bncl bcl || and fp, fp and fp, fp bncl.s bcl .text .global bra__cmpbra__cmp: bra bcl || cmp fp, fp cmp fp, fp# Use bra.s here as bra is relaxable and thus the parallelization won't happen. bra.s bcl .text .global jl__cmpeqjl__cmpeq: jl fp || cmpeq fp, fp cmpeq fp, fp jl fp .text .global jmp__cmpujmp__cmpu: jmp fp || cmpu fp, fp cmpu fp, fp jmp fp .text .global ld__cmpzld__cmpz: ld fp, @fp || cmpz r1 cmpz r1 ld fp, @fp .text .global ld__ldild__ldi: ld fp, @r1+ || ldi r2, #77 ld fp, @r1+ ldi r2, #77 .text .global ldb__mvldb__mv: ldb fp, @fp || mv r2, fp ldb fp, @fp mv r2, fp .text .global ldh__negldh__neg: ldh fp, @fp || neg r2, fp ldh fp, @fp neg r2, fp .text .global ldub__nopldub__nop: ldub fp, @fp || nop ldub fp, @fp nop .text .global lduh__notlduh__not: lduh fp, @fp || not r2, fp lduh fp, @fp not r2, fp .text .global lock__orlock__or: lock fp, @fp || or r2, fp lock fp, @fp or r2, fp .text .global mvfc__submvfc__sub: mvfc fp, cr1 || sub r2, fp mvfc fp, cr1 sub r2, fp .text .global mvtc__subvmvtc__subv: mvtc fp, cr2 || subv r2, fp mvtc fp, cr2 subv r2, fp .text .global rte__subxrte__subx: rte || sub r2, fp rte subx r2, fp .text .global sll__xorsll__xor: sll fp, r1 || xor r2, fp sll fp, r1 xor r2, fp .text .global slli__machislli__machi: slli fp, #22 || machi r2, fp slli fp, #22 machi r2, fp .text .global sra__maclh1sra__maclh1: sra fp, fp || maclh1 r2, fp sra fp, fp maclh1 r2, fp .text .global srai__maclosrai__maclo: srai fp, #22 || maclo r2, fp srai fp, #22 maclo r2, fp .text .global srl__macwhisrl__macwhi: srl fp, fp || macwhi r2, fp srl fp, fp macwhi r2, fp .text .global srli__macwlosrli__macwlo: srli fp, #22 || macwlo r2, fp srli fp, #22 macwlo r2, fp .text .global st__macwu1st__macwu1: st fp, @fp || macwu1 r2, fp st fp, @fp macwu1 r2, fp .text .global st__msblost__msblo: st fp, @+fp || msblo r2, fp st fp, @+fp msblo r2, fp .text .global st__mulst__mul: st fp, @-fp || mul r2, fp st fp, @-fp mul r2, fp .text .global stb__mulhistb__mulhi: stb fp, @fp || mulhi r2, fp stb fp, @fp mulhi r2, fp .text .global sth__mullosth__mullo: sth fp, @fp || mullo r2, fp sth fp, @fp mullo r2, fp .text .global trap__mulwhitrap__mulwhi: trap #2 || mulwhi r2, fp trap #2 mulwhi r2, fp .text .global unlock__mulwlounlock__mulwlo: unlock fp, @fp || mulwlo r2, fp unlock fp, @fp mulwlo r2, fp .text .global add__mulwu1add__mulwu1: add fp, fp || mulwu1 r2, fp add fp, fp mulwu1 r2, fp .text .global addi__mvfachiaddi__mvfachi: addi fp, #77 || mvfachi r2, a0 addi fp, #77 mvfachi r2, a0 .text .global addv__mvfacloaddv__mvfaclo: addv fp, fp || mvfaclo r2, a1 addv fp, fp mvfaclo r2, a1 .text .global addx__mvfacmiaddx__mvfacmi: addx fp, fp || mvfacmi r2, a0 addx fp, fp mvfacmi r2, a0 .text .global and__mvtachiand__mvtachi: and fp, fp || mvtachi r2, a0 and fp, fp mvtachi r2, a0 .text .global cmp__mvtaclocmp__mvtaclo: cmp fp, fp || mvtaclo r2, a0 cmp fp, fp mvtaclo r2, a0 .text .global cmpeq__raccmpeq__rac: cmpeq fp, fp || rac a1 cmpeq fp, fp rac a1 .text .global cmpu__rachcmpu__rach: cmpu fp, fp || rach a0, a1 cmpu fp, fp rach a1, a1, #1 .text .global cmpz__saddcmpz__sadd: cmpz fp || sadd cmpz fp sadd # Test private instructions .text .global scsc: sc sadd .text .global sncsnc: snc sadd .text .global jcjc: jc fp .text .global jncjnc: jnc fp .text .global pcmpbzpcmpbz: pcmpbz fp .text .global satsat: sat fp, fp .text .global sathsath: sath fp, fp # Test parallel versions of the private instructions .text .global jc__pcmpbzjc__pcmpbz: jc fp || pcmpbz fp jc fp pcmpbz fp .text .global jnc__ldijnc__ldi: jnc fp || ldi fp, #77 jnc fp ldi fp, #77 .text .global sc__mvsc__mv: sc || mv fp, r2 sc mv fp, r2 .text .global snc__negsnc__neg: snc || neg fp, r2 snc neg fp, r2 # Test automatic and explicit parallelisation of instructions .text .global nop__saddnop__sadd: nop sadd .text .global sadd__nopsadd__nop: sadd nop .text .global sadd__nop_reversesadd__nop_reverse: sadd || nop .text .global add__notadd__not: add r0, r1 not r3, r5 .text .global add__not__dest_clashadd__not_dest_clash: add r3, r4 not r3, r5 .text .global add__not__src_clashadd__not__src_clash: add r3, r4 not r5, r3 .text .global add__not__no_clashadd__not__no_clash: add r3, r4 not r4, r5 .text .global mul__sramul__sra: mul r1, r2 sra r3, r4 .text .global mul__sra__reverse_src_clashmul__sra__reverse_src_clash: mul r1, r3 sra r3, r4 .text .global bc__add_bc__add_: bc.s label add r1, r2 .text .global add__bcadd__bc: add r3, r4 bc.s label .text .global bc__add__forced_parallelbc__add__forced_parallel: bc label || add r5, r6 .text .global add__bc__forced_paralleladd__bc__forced_parallel: add r7, r8 || bc labellabel: nop; Additional testcases.; These insns were added to the chip later. .textmulwhi: mulwhi fp, fp, a0 mulwhi fp, fp, a1 mulwlo: mulwlo fp, fp, a0 mulwlo fp, fp, a1macwhi: macwhi fp, fp, a0 macwhi fp, fp, a1macwlo: macwlo fp, fp, a0 macwlo fp, fp, a1⌨️ 快捷键说明
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