📄 am33-2.c
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dreg (4, 1), comma, lparen, amreg (12), comma, amreg (8), rparen);def_am_insn (fmov, d8rfd, 4, 0xfba0, lparen, d8 (0), comma, amreg (12), rparen, comma, dreg (8, 16));def_am_insn (fmov, rpi8fd, 4, 0xfba2, lparen, amreg (12), plus, comma, d8 (0), rparen, comma, dreg (8, 16));def_am_insn (fmov, d8spfd, 4, 0xfba4, lparen, u8 (0), comma, spreg, rparen, comma, dreg (8, 16), tick_random);def_am_insn (fmov, fdd8r, 4, 0xfbb0, dreg (12, 17), comma, lparen, d8 (0), comma, amreg (8), rparen);def_am_insn (fmov, fdrpi8, 4, 0xfbb1, dreg (12, 17), comma, lparen, amreg (8), plus, comma, d8 (0), rparen);def_am_insn (fmov, fdi8sp, 4, 0xfbb4, dreg (12, 17), comma, lparen, u8 (0), comma, spreg, rparen, tick_random);def_am_insn (fmov, d24rfd, 6, 0xfda0, lparen, d24 (0), comma, amreg (28), rparen, comma, dreg (24, 32));def_am_insn (fmov, rpi24fd, 6, 0xfda2, lparen, amreg (28), plus, comma, d24 (0), rparen, comma, dreg (24, 32));def_am_insn (fmov, d24spfd, 6, 0xfda4, lparen, u24 (0), comma, spreg, rparen, comma, dreg (24, 32), tick_random);def_am_insn (fmov, fdd24r, 6, 0xfdb0, dreg (28, 33), comma, lparen, d24 (0), comma, amreg (24), rparen);def_am_insn (fmov, fdrpi24, 6, 0xfdb1, dreg (28, 33), comma, lparen, amreg (24), plus, comma, d24 (0), rparen);def_am_insn (fmov, fdd24sp, 6, 0xfdb4, dreg (28, 33), comma, lparen, u24 (0), comma, spreg, rparen, tick_random);def_am_insn (fmov, d32rfd, 7, 0xfe40, lparen, d32 (0), comma, amreg (36), rparen, comma, dreg (32, 40));def_am_insn (fmov, rpi32fd, 7, 0xfe42, lparen, amreg (36), plus, comma, d32 (0), rparen, comma, dreg (32, 40));def_am_insn (fmov, d32spfd, 7, 0xfe44, lparen, d32 (0), comma, spreg, rparen, comma, dreg (32, 40), tick_random);def_am_insn (fmov, fdd32r, 7, 0xfe50, dreg (36, 41), comma, lparen, d32 (0), comma, amreg (32), rparen);def_am_insn (fmov, fdrpi32, 7, 0xfe51, dreg (36, 41), comma, lparen, amreg (32), plus, comma, d32 (0), rparen);def_am_insn (fmov, fdd32sp, 7, 0xfe54, dreg (36, 41), comma, lparen, d32 (0), comma, spreg, rparen, tick_random);/* Define the group of double-precision FP move insns. */func *fmovd_insns[] = { am_insn (fmov, irfd), am_insn (fmov, rpfd), am_insn (fmov, spfd), am_insn (fmov, fdir), am_insn (fmov, fdrp), am_insn (fmov, fdsp), am_insn (fmov, fdfd), am_insn (fmov, irrfd), am_insn (fmov, fdirr), am_insn (fmov, d8rfd), am_insn (fmov, rpi8fd), am_insn (fmov, d8spfd), am_insn (fmov, fdd8r), am_insn (fmov, fdrpi8), am_insn (fmov, fdi8sp), am_insn (fmov, d24rfd), am_insn (fmov, rpi24fd), am_insn (fmov, d24spfd), am_insn (fmov, fdd24r), am_insn (fmov, fdrpi24), am_insn (fmov, fdd24sp), am_insn (fmov, d32rfd), am_insn (fmov, rpi32fd), am_insn (fmov, d32spfd), am_insn (fmov, fdd32r), am_insn (fmov, fdrpi32), am_insn (fmov, fdd32sp), 0};/* Define fmov FPCR insns. */def_am_insn (fmov, vrfc, 3, 0xf9b5, amreg (4), comma, fcreg);def_am_insn (fmov, fcvr, 3, 0xf9b7, fcreg, comma, amreg (0));def_am_insn (fmov, i32fc, 6, 0xfdb5, d32 (0), comma, fcreg);/* Define the group of FPCR move insns. */func *fmovc_insns[] = { am_insn (fmov, vrfc), am_insn (fmov, fcvr), am_insn (fmov, i32fc), 0};/* Define single-precision floating-point arithmetic insns. */def_am_insn (fabs, fs, 3, 0xf944, freg (0, 8));def_am_insn (fabs, fsfs, 4, 0xfb44, freg (12, 3), comma, freg (4, 1), tick_random);def_am_insn (fneg, fs, 3, 0xf946, freg (0, 8));def_am_insn (fneg, fsfs, 4, 0xfb46, freg (12, 3), comma, freg (4, 1), tick_random);def_am_insn (frsqrt, fs, 3, 0xf950, freg (0, 8));def_am_insn (frsqrt, fsfs, 4, 0xfb50, freg (12, 3), comma, freg (4, 1), tick_random);def_am_insn (fsqrt, fs, 3, 0xf952, freg (0, 8));def_am_insn (fsqrt, fsfs, 4, 0xfb54, freg (12, 3), comma, freg (4, 1), tick_random);def_am_insn (fcmp, fsfs, 3, 0xf954, freg (4, 9), comma, freg (0, 8), tick_random);def_am_insn (fcmp, i32fs, 7, 0xfe35, d32 (0), comma, freg (36, 41), tick_random);def_am_insn (fadd, fsfs, 3, 0xf960, freg (4, 9), comma, freg (0, 8), tick_random);def_am_insn (fadd, fsfsfs, 4, 0xfb60, freg (12, 3), comma, freg (8, 2), comma, freg (4, 1));def_am_insn (fadd, i32fsfs, 7, 0xfe60, d32 (0), comma, freg (36, 41), comma, freg (32, 40));def_am_insn (fsub, fsfs, 3, 0xf964, freg (4, 9), comma, freg (0, 8), tick_random);def_am_insn (fsub, fsfsfs, 4, 0xfb64, freg (12, 3), comma, freg (8, 2), comma, freg (4, 1));def_am_insn (fsub, i32fsfs, 7, 0xfe64, d32 (0), comma, freg (36, 41), comma, freg (32, 40));def_am_insn (fmul, fsfs, 3, 0xf970, freg (4, 9), comma, freg (0, 8), tick_random);def_am_insn (fmul, fsfsfs, 4, 0xfb70, freg (12, 3), comma, freg (8, 2), comma, freg (4, 1));def_am_insn (fmul, i32fsfs, 7, 0xfe70, d32 (0), comma, freg (36, 41), comma, freg (32, 40));def_am_insn (fdiv, fsfs, 3, 0xf974, freg (4, 9), comma, freg (0, 8), tick_random);def_am_insn (fdiv, fsfsfs, 4, 0xfb74, freg (12, 3), comma, freg (8, 2), comma, freg (4, 1));def_am_insn (fdiv, i32fsfs, 7, 0xfe74, d32 (0), comma, freg (36, 41), comma, freg (32, 40));/* Define the group of single-precision floating-point arithmetic insns. */func *sfparith_insns[] = { am_insn (fabs, fs), am_insn (fabs, fsfs), am_insn (fneg, fs), am_insn (fneg, fsfs), am_insn (frsqrt, fs), am_insn (frsqrt, fsfs), am_insn (fsqrt, fs), am_insn (fsqrt, fsfs), am_insn (fcmp, fsfs), am_insn (fcmp, i32fs), am_insn (fadd, fsfs), am_insn (fadd, fsfsfs), am_insn (fadd, i32fsfs), am_insn (fsub, fsfs), am_insn (fsub, fsfsfs), am_insn (fsub, i32fsfs), am_insn (fmul, fsfs), am_insn (fmul, fsfsfs), am_insn (fmul, i32fsfs), am_insn (fdiv, fsfs), am_insn (fdiv, fsfsfs), am_insn (fdiv, i32fsfs), 0};/* Define floating-point accumulator arithmetic insns. */def_am_insn (fmadd, , 4, 0xfb80, freg (12, 3), comma, freg (8, 2), comma, freg (4, 1), comma, areg (16, 0), tick_random);def_am_insn (fmsub, , 4, 0xfb84, freg (12, 3), comma, freg (8, 2), comma, freg (4, 1), comma, areg (16, 0), tick_random);def_am_insn (fnmadd, , 4, 0xfb90, freg (12, 3), comma, freg (8, 2), comma, freg (4, 1), comma, areg (16, 0), tick_random);def_am_insn (fnmsub, , 4, 0xfb94, freg (12, 3), comma, freg (8, 2), comma, freg (4, 1), comma, areg (16, 0), tick_random);/* Define the group of floating-point accumulator arithmetic insns. */func *fpacc_insns[] = { am_insn (fmadd, ), am_insn (fmsub, ), am_insn (fnmadd, ), am_insn (fnmsub, ), 0};/* Define double-precision floating-point arithmetic insns. */def_am_insn (fabs, fd, 3, 0xf9c4, dreg (0, 8));def_am_insn (fabs, fdfd, 4, 0xfbc4, dreg (12, 3), comma, dreg (4, 1), tick_random);def_am_insn (fneg, fd, 3, 0xf9c6, dreg (0, 8));def_am_insn (fneg, fdfd, 4, 0xfbc6, dreg (12, 3), comma, dreg (4, 1), tick_random);def_am_insn (frsqrt, fd, 3, 0xf9d0, dreg (0, 8));def_am_insn (frsqrt, fdfd, 4, 0xfbd0, dreg (12, 3), comma, dreg (4, 1), tick_random);def_am_insn (fsqrt, fd, 3, 0xf9d2, dreg (0, 8));def_am_insn (fsqrt, fdfd, 4, 0xfbd4, dreg (12, 3), comma, dreg (4, 1), tick_random);def_am_insn (fcmp, fdfd, 3, 0xf9d4, dreg (4, 9), comma, dreg (0, 8), tick_random);def_am_insn (fadd, fdfd, 3, 0xf9e0, dreg (4, 9), comma, dreg (0, 8), tick_random);def_am_insn (fadd, fdfdfd, 4, 0xfbe0, dreg (12, 3), comma, dreg (8, 2), comma, dreg (4, 1));def_am_insn (fsub, fdfd, 3, 0xf9e4, dreg (4, 9), comma, dreg (0, 8), tick_random);def_am_insn (fsub, fdfdfd, 4, 0xfbe4, dreg (12, 3), comma, dreg (8, 2), comma, dreg (4, 1));def_am_insn (fmul, fdfd, 3, 0xf9f0, dreg (4, 9), comma, dreg (0, 8), tick_random);def_am_insn (fmul, fdfdfd, 4, 0xfbf0, dreg (12, 3), comma, dreg (8, 2), comma, dreg (4, 1));def_am_insn (fdiv, fdfd, 3, 0xf9f4, dreg (4, 9), comma, dreg (0, 8), tick_random);def_am_insn (fdiv, fdfdfd, 4, 0xfbf4, dreg (12, 3), comma, dreg (8, 2), comma, dreg (4, 1));/* Define the group of double-precision floating-point arithmetic insns. */func *dfparith_insns[] = { am_insn (fabs, fd), am_insn (fabs, fdfd), am_insn (fneg, fd), am_insn (fneg, fdfd), am_insn (frsqrt, fd), am_insn (frsqrt, fdfd), am_insn (fsqrt, fd), am_insn (fsqrt, fdfd), am_insn (fcmp, fdfd), am_insn (fadd, fdfd), am_insn (fadd, fdfdfd), am_insn (fsub, fdfd), am_insn (fsub, fdfdfd), am_insn (fmul, fdfd), am_insn (fmul, fdfdfd), am_insn (fdiv, fdfd), am_insn (fdiv, fdfdfd), 0};/* Define floating-point conversion insns. */def_am_insn (ftoi, fsfs, 4, 0xfb40, freg (12, 3), comma, freg (4, 1), tick_random);def_am_insn (itof, fsfs, 4, 0xfb42, freg (12, 3), comma, freg (4, 1), tick_random);def_am_insn (ftod, fsfd, 4, 0xfb52, freg (12, 3), comma, dreg (4, 1), tick_random);def_am_insn (dtof, fdfs, 4, 0xfb56, dreg (12, 3), comma, freg (4, 1), tick_random);/* Define the group of floating-point conversion insns. */func *fpconv_insns[] = { am_insn (ftoi, fsfs), am_insn (itof, fsfs), am_insn (ftod, fsfd), am_insn (dtof, fdfs), 0};/* Define conditional jump insns. */def_am_insn (fbeq, , 3, 0xf8d0, d8pcsec (0));def_am_insn (fbne, , 3, 0xf8d1, d8pcsec (0));def_am_insn (fbgt, , 3, 0xf8d2, d8pcsec (0));def_am_insn (fbge, , 3, 0xf8d3, d8pcsec (0));def_am_insn (fblt, , 3, 0xf8d4, d8pcsec (0));def_am_insn (fble, , 3, 0xf8d5, d8pcsec (0));def_am_insn (fbuo, , 3, 0xf8d6, d8pcsec (0));def_am_insn (fblg, , 3, 0xf8d7, d8pcsec (0));def_am_insn (fbleg,, 3, 0xf8d8, d8pcsec (0));def_am_insn (fbug, , 3, 0xf8d9, d8pcsec (0));def_am_insn (fbuge,, 3, 0xf8da, d8pcsec (0));def_am_insn (fbul, , 3, 0xf8db, d8pcsec (0));def_am_insn (fbule,, 3, 0xf8dc, d8pcsec (0));def_am_insn (fbue, , 3, 0xf8dd, d8pcsec (0));def_am_insn (fleq, , 2, 0xf0d0, nothing);def_am_insn (flne, , 2, 0xf0d1, nothing);def_am_insn (flgt, , 2, 0xf0d2, nothing);def_am_insn (flge, , 2, 0xf0d3, nothing);def_am_insn (fllt, , 2, 0xf0d4, nothing);def_am_insn (flle, , 2, 0xf0d5, nothing);def_am_insn (fluo, , 2, 0xf0d6, nothing);def_am_insn (fllg, , 2, 0xf0d7, nothing);def_am_insn (flleg,, 2, 0xf0d8, nothing);def_am_insn (flug, , 2, 0xf0d9, nothing);def_am_insn (fluge,, 2, 0xf0da, nothing);def_am_insn (flul, , 2, 0xf0db, nothing);def_am_insn (flule,, 2, 0xf0dc, nothing);def_am_insn (flue, , 2, 0xf0dd, nothing);/* Define the group of conditional jump insns. */func *condjmp_insns[] = { am_insn (fbeq, ), am_insn (fbne, ), am_insn (fbgt, ), am_insn (fbge, ), am_insn (fblt, ), am_insn (fble, ), am_insn (fbuo, ), am_insn (fblg, ), am_insn (fbleg, ), am_insn (fbug, ), am_insn (fbuge, ), am_insn (fbul, ), am_insn (fbule, ), am_insn (fbue, ), am_insn (fleq, ), am_insn (flne, ), am_insn (flgt, ), am_insn (flge, ), am_insn (fllt, ), am_insn (flle, ), am_insn (fluo, ), am_insn (fllg, ), am_insn (flleg, ), am_insn (flug, ), am_insn (fluge, ), am_insn (flul, ), am_insn (flule, ), am_insn (flue, ), 0};/* Define the set of all groups. */group_tgroups[] = { { "dcpf", dcpf_insns }, { "bit", bit_insns }, { "fmovs", fmovs_insns }, { "fmovd", fmovd_insns }, { "fmovc", fmovc_insns }, { "sfparith", sfparith_insns }, { "fpacc", fpacc_insns }, { "dfparith", dfparith_insns }, { "fpconv", fpconv_insns }, { "condjmp", condjmp_insns }, { 0 }};intmain(int argc, char *argv[]){ FILE *as_in = stdout, *dis_out = stderr; /* Check whether we're filtering insns. */ if (argc > 1) skip_list = argv + 1; /* Output assembler header. */ fputs ("\t.text\n" "\t.am33_2\n", as_in); /* Output comments for the testsuite-driver and the initial * disassembler output. */ fputs ("#objdump: -dr --prefix-address --show-raw-insn\n" "#name: AM33/2.0\n" "\n" ".*: +file format.*elf32-mn10300.*\n" "\n" "Disassembly of section .text:\n", dis_out); /* Now emit all (selected) insns. */ output_groups (groups, as_in, dis_out); exit (0);}
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