am33-2.c

GNU binutils是GNU交叉工具链中的一个源码包

/* Copyright (C) 2000, 2002 Free Software Foundation
 * Contributed by Alexandre Oliva <[e-mail]>
 *
 * This file is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 */

/* Generator of tests for insns introduced in AM33 2.0.  */

#define INSN_REPEAT 11

/* See the following file for usage and documentation.  */
#include "../all/test-gen.c"

/* These are the AM33 registers.  */
const char *am33_regs[] = {
  /* These are the canonical names, i.e., those printed by the
   * disassembler.  */
  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  "a0", "a1", "a2", "a3", "d0", "d1", "d2", "d3",
  /* These are aliases that the assembler should also recognize.  */
  "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7",
  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
};

/* Signed constants of the given sizes.  */
#define  d8(shift) signed_constant( 8, shift, 1)
#define d16(shift) signed_constant(16, shift, 1)
#define d24(shift) signed_constant(24, shift, 1)
#define d32(shift) signed_constant(32, shift, 1)
#define  u8(shift) unsigned_constant( 8, shift, 1)
#define u24(shift) unsigned_constant(24, shift, 1)
#define a16(shift) absolute_address(16, shift, 1)

/* Emit an AM33 register shifted by these many words. */
#define amreg(shift) reg_r (am33_regs, shift, 15, mk_get_bits (5u))
#define spreg literal ("sp")
#define fcreg literal ("fpcr")

/* Emit an AM33-2 FP single-precision register, with the 4 least
 * significant bits shifted by shiftlow and the most significant bit
 * shifted by shifthigh.  */
int
freg (func_arg *arg, insn_data *data)
#define freg(shiftlow, shifthigh) { freg, { i1: shiftlow, i2: shifthigh } }
{
  unsigned val = get_bits (5u);

  data->as_in = data->dis_out = (char*)malloc (3 + ulen (val, 10));
  sprintf (data->as_in, "fs%u", val);
  data->bits = val;
  data->bits = ((data->bits & 15) << arg->i1) | ((data->bits >> 4) << arg->i2);

  return 0;
}

/* Emit an AM33-2 FP single-precision register in the ``accumulator''
 * range, with the 2 least significant bits shifted by shiftlow and
 * the most significant bit shifted by shifthigh. */
int
areg (func_arg *arg, insn_data *data)
#define areg(shiftlow, shifthigh) { areg, { i1: shiftlow, i2: shifthigh } }
{
  unsigned val = get_bits (3u);

  data->as_in = data->dis_out = (char*)malloc (4);
  sprintf (data->as_in, "fs%u", val);
  data->bits = val;
  data->bits = ((data->bits & 3) << arg->i1) | ((data->bits >> 2) << arg->i2);

  return 0;
}

/* Emit an AM33-2 FP double-precision register, with the 4 least
 * significant bits shifted by shiftlow and the most significant bit
 * shifted by shifthigh. */
int
dreg (func_arg *arg, insn_data *data)
#define dreg(shiftlow, shifthigh) { dreg, { i1: shiftlow, i2: shifthigh } }
{
  unsigned val = 2 * get_bits (4u);

  data->as_in = data->dis_out = (char*)malloc (3 + ulen (val, 10));
  sprintf (data->as_in, "fd%u", val);
  data->bits = val;
  data->bits = ((data->bits & 15) << arg->i1) | ((data->bits >> 4) << arg->i2);

  return 0;
}

/* Emit a signed 8-bit PC-relative offset from the current insn to the
 * last emitted label.  */
int
d8pcoff (func_arg *arg, insn_data *data)
#define  d8pcoff(shift) { d8pcoff, { p1: shift } }
{
  int diff = insn_size - arg->i1/8 - 1;
  int displacement = current_offset - last_label_offset;
  char *current_address = malloc (strlen (last_label_name) + 4
				  + ulen (displacement, 16) + 1);

  /* Make sure we're not too far from the target.  */
  if (displacement > 128)
    abort ();

  data->as_in = strdup (last_label_name);

  /* Calculate the address that will be printed by the disassembler as
     the target of the jump.  Since it won't take relocations into
     account, it will be the insn's own address.  */
  if (current_offset == last_label_offset)
    strcpy (current_address, last_label_name);
  else
    sprintf (current_address, "%s\\+0x%x", last_label_name, displacement);

  /* Compute the complete label, including the relocation message
     printed as an additional message.  The relocation will point us
     to the intended target label plus an offset equal to the offset
     of the displacement within the current insn.  We do not account
     for the case in which this displacement is zero, since it doesn't
     come up on this platform. */
  data->dis_out = malloc (8 + 2 + strlen (current_address) + 2
			  + 3 + ulen (current_offset + diff, 16) + 19
			  + strlen (last_label_name) + 4
			  + ulen (diff, 16) + 1);
  sprintf (data->dis_out, "0*%x <%s>\n"
	   "\t\t\t%x: R_MN10300_PCREL8\t%s\\+0x%x",
	   current_offset, current_address,
	   current_offset + diff, last_label_name, diff);

  free (current_address);

  return 0;
}

/* Emit a signed 8-bit PC-relative offset from the current insn to the
 * current section.  */
int
d8pcsec (func_arg *arg, insn_data *data)
#define  d8pcsec(shift) { d8pcsec, { p1: shift } }
{
  int diff = insn_size - arg->i1/8 - 1;
  int displacement = current_offset - last_label_offset;
  char *current_address = malloc (strlen (last_label_name) + 4
				  + ulen (displacement, 16) + 1);

  /* Make sure we're not too far from the target.  */
  if (displacement > 128)
    abort ();

  data->as_in = strdup (last_label_name);

  /* Calculate the address that will be printed by the disassembler as
     the target of the jump.  Since it won't take relocations into
     account, it will be the insn's own address.  */

  if (current_offset == last_label_offset)
    strcpy (current_address, last_label_name);
  else
    sprintf (current_address, "%s\\+0x%x", last_label_name, displacement);


  /* Compute the complete label, including the relocation message
     printed as an additional message.  The relocation will point us
     to the intended target label plus an offset equal to the offset
     of the displacement within the current insn.  We do not account
     for the case in which this displacement is zero, since it doesn't
     come up on this platform. */
  data->dis_out = malloc (8 + 2 + strlen (current_address) + 2
			  + 3 + ulen (current_offset + diff, 16) + 33);
  sprintf (data->dis_out, "0*%x <%s>\n"
	   "\t\t\t%x: R_MN10300_PCREL8\tcondjmp\\+0x2",
	   current_offset, current_address,
	   current_offset + diff);

  free (current_address);

  return 0;
}

/* Convenience wrapper to define_insn.  */
#define def_am_insn(insname, variant, size, word, funcs...) \
  define_insn(insname ## _ ## variant, \
	      insn_size_bits (insname, size, \
			      ((unsigned long long)word) << 8*(size-2)), \
	      tab, \
	      ## funcs)
#define am_insn(insname, variant) insn (insname ## _ ## variant)

#define def_bit_insn(insname, word) \
  def_am_insn (insname, i8a16, 5, word, \
	       u8(0), comma, lparen, a16 (8), rparen, tick_random);
#define bit_insn(insname) insn (insname ## _ ## i8a16)

/* Data cache pre-fetch insns.  */
def_am_insn (dcpf, r,    3, 0xf9a6, lparen, amreg (4), rparen);
def_am_insn (dcpf, sp,   3, 0xf9a7, lparen, spreg, rparen);
def_am_insn (dcpf, rr,   4, 0xfba6,
	     lparen, amreg(12), comma, amreg (8), rparen, tick_random);
def_am_insn (dcpf, d8r,  4, 0xfba7,
	     lparen, d8 (0), comma, amreg (12), rparen, tick_random);
def_am_insn (dcpf, d24r, 6, 0xfda7,
	     lparen, d24(0), comma, amreg (28), rparen, tick_random);
def_am_insn (dcpf, d32r, 7, 0xfe46,
	     lparen, d32(0), comma, amreg (36), rparen, tick_random);

/* Define the group of data cache pre-fetch insns.  */
func *dcpf_insns[] = {
  am_insn (dcpf, r),
  am_insn (dcpf, sp),
  am_insn (dcpf, rr),
  am_insn (dcpf, d8r),
  am_insn (dcpf, d24r),
  am_insn (dcpf, d32r),
  0
};

/* Bit operations.  */
def_bit_insn (bset, 0xfe80);
def_bit_insn (bclr, 0xfe81);
def_bit_insn (btst, 0xfe82);

/* Define the group of bit insns.  */
func *bit_insns[] = {
  bit_insn (bset),
  bit_insn (bclr),
  bit_insn (btst),
  0
};

/* Define the single-precision FP move insns.  */
def_am_insn (fmov, irfs, 3, 0xf920,
	     lparen, amreg (4), rparen, comma,
	     freg (0, 8), tick_random);
def_am_insn (fmov, rpfs, 3, 0xf922,
	     lparen, amreg (4), plus, rparen, comma,
	     freg (0, 8), tick_random);
def_am_insn (fmov, spfs, 3, 0xf924,
	     lparen, spreg, rparen, comma, freg (0, 8));
def_am_insn (fmov, vrfs, 3, 0xf926,
	     amreg (4), comma, freg (0, 8), tick_random);
def_am_insn (fmov, fsir, 3, 0xf930,
	     freg (4, 9), comma, lparen, amreg (0), rparen, tick_random);
def_am_insn (fmov, fsrp, 3, 0xf931,
	     freg (4, 9), comma, lparen, amreg (0), plus, rparen, tick_random);
def_am_insn (fmov, fssp, 3, 0xf934,
	     freg (4, 9), comma, lparen, spreg, rparen);
def_am_insn (fmov, fsvr, 3, 0xf935,
	     freg (4, 9), comma, amreg (0), tick_random);
def_am_insn (fmov, fsfs, 3, 0xf940,
	     freg (4, 9), comma, freg (0, 8), tick_random);
def_am_insn (fmov, d8rfs, 4, 0xfb20,
	     lparen, d8 (0), comma, amreg (12), rparen, comma,
	     freg (8, 16));
def_am_insn (fmov, rpi8fs, 4, 0xfb22,
	     lparen, amreg (12), plus, comma, d8 (0), rparen, comma,
	     freg (8, 16));
def_am_insn (fmov, d8spfs, 4, 0xfb24,
	     lparen, u8 (0), comma, spreg, rparen, comma, freg (8, 16),
	     tick_random);
def_am_insn (fmov, irrfs, 4, 0xfb27,
	     lparen, amreg (12), comma, amreg (8), rparen, comma,
	     freg (4, 1));
def_am_insn (fmov, fsd8r, 4, 0xfb30,
	     freg (12, 17), comma, lparen, d8 (0), comma, amreg (8), rparen);
def_am_insn (fmov, fsrpi8, 4, 0xfb31,
	     freg (12, 17), comma,
	     lparen, amreg (8), plus, comma, d8 (0), rparen);
def_am_insn (fmov, fsd8sp, 4, 0xfb34,
	     freg (12, 17), comma,
	     lparen, u8 (0), comma, spreg, rparen, tick_random);
def_am_insn (fmov, fsirr, 4, 0xfb37,
	     freg (4, 1), comma,
	     lparen, amreg (12), comma, amreg (8), rparen);
def_am_insn (fmov, d24rfs, 6, 0xfd20,
	     lparen, d24 (0), comma, amreg (28), rparen, comma, freg (24, 32));
def_am_insn (fmov, rpi24fs, 6, 0xfd22,
	     lparen, amreg (28), plus, comma, d24 (0), rparen, comma,
	     freg (24, 32));
def_am_insn (fmov, d24spfs, 6, 0xfd24,
	     lparen, u24 (0), comma, spreg, rparen, comma,
	     freg (24, 32), tick_random);
def_am_insn (fmov, fsd24r, 6, 0xfd30,
	     freg (28, 33), comma, lparen, d24 (0), comma, amreg (24), rparen);
def_am_insn (fmov, fsrpi24, 6, 0xfd31,
	     freg (28, 33), comma,
	     lparen, amreg (24), plus, comma, d24 (0), rparen);
def_am_insn (fmov, fsd24sp, 6, 0xfd34,
	     freg (28, 33), comma,
	     lparen, u24 (0), comma, spreg, rparen, tick_random);
def_am_insn (fmov, d32rfs, 7, 0xfe20,
	     lparen, d32 (0), comma, amreg (36), rparen, comma, freg (32, 40));
def_am_insn (fmov, rpi32fs, 7, 0xfe22,
	     lparen, amreg (36), plus, comma, d32 (0), rparen, comma,
	     freg (32, 40));
def_am_insn (fmov, d32spfs, 7, 0xfe24,
	     lparen, d32 (0), comma, spreg, rparen, comma,
	     freg (32, 40), tick_random);
def_am_insn (fmov, i32fs, 7, 0xfe26,
	     d32 (0), comma, freg (32, 40), tick_random);
def_am_insn (fmov, fsd32r, 7, 0xfe30,
	     freg (36, 41), comma, lparen, d32 (0), comma, amreg (32), rparen);
def_am_insn (fmov, fsrpi32, 7, 0xfe31,
	     freg (36, 41), comma,
	     lparen, amreg (32), plus, comma, d32 (0), rparen);
def_am_insn (fmov, fsd32sp, 7, 0xfe34,
	     freg (36, 41), comma,
	     lparen, d32 (0), comma, spreg, rparen, tick_random);

/* Define the group of single-precision FP move insns.  */
func *fmovs_insns[] = {
  am_insn (fmov, irfs),
  am_insn (fmov, rpfs),
  am_insn (fmov, spfs),
  am_insn (fmov, vrfs),
  am_insn (fmov, fsir),
  am_insn (fmov, fsrp),
  am_insn (fmov, fssp),
  am_insn (fmov, fsvr),
  am_insn (fmov, fsfs),
  am_insn (fmov, d8rfs),
  am_insn (fmov, rpi8fs),
  am_insn (fmov, d8spfs),
  am_insn (fmov, irrfs),
  am_insn (fmov, fsd8r),
  am_insn (fmov, fsrpi8),
  am_insn (fmov, fsd8sp),
  am_insn (fmov, fsirr),
  am_insn (fmov, d24rfs),
  am_insn (fmov, rpi24fs),
  am_insn (fmov, d24spfs),
  am_insn (fmov, fsd24r),
  am_insn (fmov, fsrpi24),
  am_insn (fmov, fsd24sp),
  am_insn (fmov, d32rfs),
  am_insn (fmov, rpi32fs),
  am_insn (fmov, d32spfs),
  am_insn (fmov, i32fs),
  am_insn (fmov, fsd32r),
  am_insn (fmov, fsrpi32),
  am_insn (fmov, fsd32sp),
  0
};

/* Define the double-precision FP move insns.  */
def_am_insn (fmov, irfd, 3, 0xf9a0,
	     lparen, amreg (4), rparen, comma, dreg (0, 8), tick_random);
def_am_insn (fmov, rpfd, 3, 0xf9a2,
	     lparen, amreg (4), plus, rparen, comma, dreg (0, 8), tick_random);
def_am_insn (fmov, spfd, 3, 0xf9a4,
	     lparen, spreg, rparen, comma, dreg (0, 8));
def_am_insn (fmov, fdir, 3, 0xf9b0,
	     dreg (4, 9), comma, lparen, amreg (0), rparen, tick_random);
def_am_insn (fmov, fdrp, 3, 0xf9b1,
	     dreg (4, 9), comma, lparen, amreg (0), plus, rparen, tick_random);
def_am_insn (fmov, fdsp, 3, 0xf9b4,
	     dreg (4, 9), comma, lparen, spreg, rparen);
def_am_insn (fmov, fdfd, 3, 0xf9c0,
	     dreg (4, 9), comma, dreg (0, 8), tick_random);
def_am_insn (fmov, irrfd, 4, 0xfb47,
	     lparen, amreg (12), comma, amreg (8), rparen, comma, dreg (4, 1));
def_am_insn (fmov, fdirr, 4, 0xfb57,