timer.saf

多功能计时器,具有校准

# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.

# Signal Activity File Name: "H:/clock/timer.saf"
# Created On: "07/19/2008 20:16:23"
# Created By: "Version 6.0 Build 178 04/27/2006 SJ Full Version"
# This file was created by the Quartus(R) II Simulator with glitch filtering enabled.

FORMAT_VERSION 1;

DEFINE_FLAG TOGGLE_RATE_FROM_SIMULATION 0x1;
DEFINE_FLAG STATIC_PROBABILITY_FROM_SIMULATION 0x2;
DEFINE_FLAG TOGGLE_RATE_FROM_USER 0x4;
DEFINE_FLAG STATIC_PROBABILITY_FROM_USER 0x8;
DEFINE_FLAG TOGGLE_RATE_FROM_USER_DEFAULT 0x10;
DEFINE_FLAG STATIC_PROBABILITY_FROM_USER_DEFAULT 0x20;
DEFINE_FLAG TOGGLE_RATE_FROM_VECTORLESS_ESTIMATION 0x40;
DEFINE_FLAG STATIC_PROBABILITY_FROM_VECTORLESS_ESTIMATION 0x80;
DEFINE_FLAG TOGGLE_RATE_ASSUMED_ZERO 0x100;
DEFINE_FLAG TOGGLE_RATE_CLIPPED_TO_MAX 0x200;

BEGIN_OUTPUT_SIGNAL_INFO;

# Output Signal Information Line Format Description:

# <one or more spaces><partial output signal name><spaces>[<flags mask><spaces><toggle rate><spaces><static probability>]<;>

 adjuster:ADJUST_CONTROL;
  CLK~53 0x3 1.99e+008 0.49854;
  CLK~53clkctrl 0x3 1.99e+008 0.497005;
  CON[0] 0x3 0 0;
  CON[0]~33 0x3 0 0.999667;
  CON[1] 0x3 0 0;
  CON[1]~32 0x3 0 0;
  Mux3~11 0x3 0 0;
 CLK1HZ 0x3 1.99e+008 0.5;
 display:DIS_LED5;
  Mux0~19 0x3 0 0;
  Mux1~17 0x3 0 0;
  Mux2~13 0x3 0 0;
  Mux3~17 0x3 0 0;
  Mux4~23 0x3 0 0;
  Mux5~21 0x3 0 0;
  Mux6~19 0x3 0 0;
 display:DIS_LED6;
  Mux0~19 0x3 0 0;
  Mux1~17 0x3 0 0;
  Mux2~13 0x3 0 0;
  Mux3~17 0x3 0 0;
  Mux4~23 0x3 0 0;
  Mux5~21 0x3 0 0;
  Mux6~19 0x3 0 0;
 counter24:HOUR_CONTROL;
  Add1~60 0x3 0 0;
  Add1~61 0x3 0 0;
  Add1~64 0x3 0 0;
  Add1~65 0x3 0 0;
  Add1~68 0x3 0 0;
  Add1~69 0x3 0 0;
  Add1~72 0x3 0 0;
  CLR~0 0x3 0 0;
  CLR~26 0x3 0 0;
  Equal0~26 0x3 0 0;
  HIGH_REG[0] 0x3 0 0;
  HIGH_REG[1] 0x3 0 0;
  HIGH_REG[2] 0x3 0 0;
  HIGH_REG[3] 0x3 0 0;
  HIGH_REG~284 0x3 0 0;
  LOW_REG[0] 0x3 0 0;
  LOW_REG[0]~125 0x3 0 0.999667;
  LOW_REG[1] 0x3 0 0;
  LOW_REG[2] 0x3 0 0;
  LOW_REG[3] 0x3 0 0;
  LOW_REG~122 0x3 0 0;
  LOW_REG~123 0x3 0 0;
  LOW_REG~124 0x3 0 0;
 LED1[0] 0x3 0 0.997846;
 LED1[1] 0x3 0 0.997856;
 LED1[2] 0x3 0 0.997856;
 LED1[3] 0x3 0 0.997866;
 LED1[4] 0x3 0 0.998048;
 LED1[5] 0x3 0 0.997866;
 LED1[6] 0x3 0 0;
 LED2[0] 0x3 0 0.998058;
 LED2[1] 0x3 0 0.997846;
 LED2[2] 0x3 0 0.997856;
 LED2[3] 0x3 0 0.998048;
 LED2[4] 0x3 0 0.997896;
 LED2[5] 0x3 0 0.998038;
 LED2[6] 0x3 0 0;
 LED3[0] 0x3 0 0.998058;
 LED3[1] 0x3 0 0.998018;
 LED3[2] 0x3 0 0.997846;
 LED3[3] 0x3 0 0.997846;
 LED3[4] 0x3 0 0.997896;
 LED3[5] 0x3 0 0.998028;
 LED3[6] 0x3 0 0;
 LED4[0] 0x3 0 0.998018;
 LED4[1] 0x3 0 0.997846;
 LED4[2] 0x3 0 0.997866;
 LED4[3] 0x3 0 0.997846;
 LED4[4] 0x3 0 0.997866;
 LED4[5] 0x3 0 0.998002;
 LED4[6] 0x3 0 0;
 LED5[0] 0x3 0 0.996204;
 LED5[1] 0x3 0 0.996337;
 LED5[2] 0x3 0 0.996308;
 LED5[3] 0x3 0 0.996304;
 LED5[4] 0x3 0 0.996329;
 LED5[5] 0x3 0 0.996277;
 LED5[6] 0x3 0 0;
 LED6[0] 0x3 0 0.996289;
 LED6[1] 0x3 0 0.995372;
 LED6[2] 0x3 0 0.996327;
 LED6[3] 0x3 0 0.996519;
 LED6[4] 0x3 0 0.99627;
 LED6[5] 0x3 0 0.996253;
 LED6[6] 0x3 0 0;
 MODE 0x3 0 0;
 MODE~clkctrl 0x3 0 0;
 SET 0x3 0 0;

END_OUTPUT_SIGNAL_INFO;

TOGGLE_PERCENTAGE 3.33333;

PERCENTAGE_OF_TIME_SIGNALS_IN_UNKNOWN_STATE 0;