counter24.vhd

多功能计时器,具有校准

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY counter24 IS
PORT(
     CLK1HZ : IN        STD_LOGIC;
     EN      : IN       STD_LOGIC;

     LOW     : OUT      STD_LOGIC_VECTOR(3 DOWNTO 0);
     HIGH    : OUT      STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END counter24;

ARCHITECTURE rtl of counter24 IS
SIGNAL LOW_REG :STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
SIGNAL HIGH_REG :STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
SIGNAL CLR : STD_LOGIC:='0';
BEGIN
LOW_PROC:PROCESS(CLK1HZ,EN,CLR)
BEGIN
IF rising_edge(CLK1HZ) THEN
IF EN='1' THEN
IF LOW_REG ="1001" OR CLR ='1' THEN
LOW_REG<="0000";
ELSE 
LOW_REG<=LOW_REG+'1';
END IF;
END IF;
END IF;
END PROCESS;
LOW<=LOW_REG;

HIGH_PROC:PROCESS(CLK1HZ,EN,CLR)
BEGIN
IF rising_edge(CLK1HZ) THEN
IF EN='1' THEN 
IF CLR='1' THEN
HIGH_REG<="0000";
ELSIF LOW_REG="1001" THEN
HIGH_REG<=HIGH_REG+'1';
END IF;
END IF;
END IF;
END PROCESS;
HIGH<=HIGH_REG;
CLR<='1' WHEN LOW_REG="0011" AND HIGH_REG="0010" ELSE
'0';
END rtl;