timer.tan.qmsg

多功能计时器,具有校准

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "MODE 16 " "Warning: Circuit may not operate. Detected 16 non-operational path(s) clocked by clock \"MODE\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "adjuster:ADJUST_CONTROL\|CON\[1\] counter24:HOUR_CONTROL\|LOW_REG\[0\] MODE 569 ps " "Info: Found hold time violation between source  pin or register \"adjuster:ADJUST_CONTROL\|CON\[1\]\" and destination pin or register \"counter24:HOUR_CONTROL\|LOW_REG\[0\]\" for clock \"MODE\" (Hold time is 569 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "3.563 ns + Largest " "Info: + Largest clock skew is 3.563 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "MODE destination 5.619 ns + Longest register " "Info: + Longest clock path from clock \"MODE\" to destination register is 5.619 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns MODE 1 CLK PIN_M2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M2; Fanout = 2; CLK Node = 'MODE'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { MODE } "NODE_NAME" } } { "top.vhd" "" { Text "F:/clock/top.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.574 ns) + CELL(0.712 ns) 2.150 ns adjuster:ADJUST_CONTROL\|CON\[0\] 2 REG LCFF_X39_Y16_N19 4 " "Info: 2: + IC(0.574 ns) + CELL(0.712 ns) = 2.150 ns; Loc. = LCFF_X39_Y16_N19; Fanout = 4; REG Node = 'adjuster:ADJUST_CONTROL\|CON\[0\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.286 ns" { MODE adjuster:ADJUST_CONTROL|CON[0] } "NODE_NAME" } } { "adjuster.vhd" "" { Text "F:/clock/adjuster.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.217 ns) + CELL(0.225 ns) 2.592 ns adjuster:ADJUST_CONTROL\|Mux0~5 3 COMB LCCOMB_X39_Y16_N22 1 " "Info: 3: + IC(0.217 ns) + CELL(0.225 ns) = 2.592 ns; Loc. = LCCOMB_X39_Y16_N22; Fanout = 1; COMB Node = 'adjuster:ADJUST_CONTROL\|Mux0~5'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.442 ns" { adjuster:ADJUST_CONTROL|CON[0] adjuster:ADJUST_CONTROL|Mux0~5 } "NODE_NAME" } } { "adjuster.vhd" "" { Text "F:/clock/adjuster.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.204 ns) + CELL(0.154 ns) 2.950 ns adjuster:ADJUST_CONTROL\|CLK 4 COMB LCCOMB_X39_Y16_N8 1 " "Info: 4: + IC(0.204 ns) + CELL(0.154 ns) = 2.950 ns; Loc. = LCCOMB_X39_Y16_N8; Fanout = 1; COMB Node = 'adjuster:ADJUST_CONTROL\|CLK'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.358 ns" { adjuster:ADJUST_CONTROL|Mux0~5 adjuster:ADJUST_CONTROL|CLK } "NODE_NAME" } } { "adjuster.vhd" "" { Text "F:/clock/adjuster.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.385 ns) + CELL(0.000 ns) 4.335 ns adjuster:ADJUST_CONTROL\|CLK~clkctrl 5 COMB CLKCTRL_G11 8 " "Info: 5: + IC(1.385 ns) + CELL(0.000 ns) = 4.335 ns; Loc. = CLKCTRL_G11; Fanout = 8; COMB Node = 'adjuster:ADJUST_CONTROL\|CLK~clkctrl'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.385 ns" { adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl } "NODE_NAME" } } { "adjuster.vhd" "" { Text "F:/clock/adjuster.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.666 ns) + CELL(0.618 ns) 5.619 ns counter24:HOUR_CONTROL\|LOW_REG\[0\] 6 REG LCFF_X14_Y9_N9 13 " "Info: 6: + IC(0.666 ns) + CELL(0.618 ns) = 5.619 ns; Loc. = LCFF_X14_Y9_N9; Fanout = 13; REG Node = 'counter24:HOUR_CONTROL\|LOW_REG\[0\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.284 ns" { adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|LOW_REG[0] } "NODE_NAME" } } { "counter24.vhd" "" { Text "F:/clock/counter24.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.573 ns ( 45.79 % ) " "Info: Total cell delay = 2.573 ns ( 45.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.046 ns ( 54.21 % ) " "Info: Total interconnect delay = 3.046 ns ( 54.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.619 ns" { MODE adjuster:ADJUST_CONTROL|CON[0] adjuster:ADJUST_CONTROL|Mux0~5 adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|LOW_REG[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.619 ns"