timer.tan.qmsg

多功能计时器,具有校准

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "adjuster:ADJUST_CONTROL\|Mux0~5 " "Info: Detected gated clock \"adjuster:ADJUST_CONTROL\|Mux0~5\" as buffer" {  } { { "adjuster.vhd" "" { Text "F:/clock/adjuster.vhd" 42 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "adjuster:ADJUST_CONTROL\|Mux0~5" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "adjuster:ADJUST_CONTROL\|CON\[1\] " "Info: Detected ripple clock \"adjuster:ADJUST_CONTROL\|CON\[1\]\" as buffer" {  } { { "adjuster.vhd" "" { Text "F:/clock/adjuster.vhd" 30 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "adjuster:ADJUST_CONTROL\|CON\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "adjuster:ADJUST_CONTROL\|CON\[0\] " "Info: Detected ripple clock \"adjuster:ADJUST_CONTROL\|CON\[0\]\" as buffer" {  } { { "adjuster.vhd" "" { Text "F:/clock/adjuster.vhd" 30 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "adjuster:ADJUST_CONTROL\|CON\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "adjuster:ADJUST_CONTROL\|CLK " "Info: Detected gated clock \"adjuster:ADJUST_CONTROL\|CLK\" as buffer" {  } { { "adjuster.vhd" "" { Text "F:/clock/adjuster.vhd" 14 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "adjuster:ADJUST_CONTROL\|CLK" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK1HZ register counter24:HOUR_CONTROL\|LOW_REG\[2\] register counter24:HOUR_CONTROL\|HIGH_REG\[1\] 487.09 MHz 2.053 ns Internal " "Info: Clock \"CLK1HZ\" has Internal fmax of 487.09 MHz between source register \"counter24:HOUR_CONTROL\|LOW_REG\[2\]\" and destination register \"counter24:HOUR_CONTROL\|HIGH_REG\[1\]\" (period= 2.053 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.869 ns + Longest register register " "Info: + Longest register to register delay is 1.869 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter24:HOUR_CONTROL\|LOW_REG\[2\] 1 REG LCFF_X14_Y9_N15 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y9_N15; Fanout = 11; REG Node = 'counter24:HOUR_CONTROL\|LOW_REG\[2\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { counter24:HOUR_CONTROL|LOW_REG[2] } "NODE_NAME" } } { "counter24.vhd" "" { Text "F:/clock/counter24.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.276 ns) + CELL(0.346 ns) 0.622 ns counter24:HOUR_CONTROL\|Equal0~26 2 COMB LCCOMB_X14_Y9_N20 3 " "Info: 2: + IC(0.276 ns) + CELL(0.346 ns) = 0.622 ns; Loc. = LCCOMB_X14_Y9_N20; Fanout = 3; COMB Node = 'counter24:HOUR_CONTROL\|Equal0~26'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.622 ns" { counter24:HOUR_CONTROL|LOW_REG[2] counter24:HOUR_CONTROL|Equal0~26 } "NODE_NAME" } } { "d:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.215 ns) + CELL(0.309 ns) 1.146 ns counter24:HOUR_CONTROL\|Add1~61 3 COMB LCCOMB_X14_Y9_N0 2 " "Info: 3: + IC(0.215 ns) + CELL(0.309 ns) = 1.146 ns; Loc. = LCCOMB_X14_Y9_N0; Fanout = 2; COMB Node = 'counter24:HOUR_CONTROL\|Add1~61'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.524 ns" { counter24:HOUR_CONTROL|Equal0~26 counter24:HOUR_CONTROL|Add1~61 } "NODE_NAME" } } { "d:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.125 ns) 1.271 ns counter24:HOUR_CONTROL\|Add1~64 4 COMB LCCOMB_X14_Y9_N2 1 " "Info: 4: + IC(0.000 ns) + CELL(0.125 ns) = 1.271 ns; Loc. = LCCOMB_X14_Y9_N2; Fanout = 1; COMB Node = 'counter24:HOUR_CONTROL\|Add1~64'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.125 ns" { counter24:HOUR_CONTROL|Add1~61 counter24:HOUR_CONTROL|Add1~64 } "NODE_NAME" } } { "d:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.390 ns) + CELL(0.053 ns) 1.714 ns counter24:HOUR_CONTROL\|HIGH_REG~284 5 COMB LCCOMB_X14_Y9_N22 1 " "Info: 5: + IC(0.390 ns) + CELL(0.053 ns) = 1.714 ns; Loc. = LCCOMB_X14_Y9_N22; Fanout = 1; COMB Node = 'counter24:HOUR_CONTROL\|HIGH_REG~284'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.443 ns" { counter24:HOUR_CONTROL|Add1~64 counter24:HOUR_CONTROL|HIGH_REG~284 } "NODE_NAME" } } { "counter24.vhd" "" { Text "F:/clock/counter24.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 1.869 ns counter24:HOUR_CONTROL\|HIGH_REG\[1\] 6 REG LCFF_X14_Y9_N23 10 " "Info: 6: + IC(0.000 ns) + CELL(0.155 ns) = 1.869 ns; Loc. = LCFF_X14_Y9_N23; Fanout = 10; REG Node = 'counter24:HOUR_CONTROL\|HIGH_REG\[1\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { counter24:HOUR_CONTROL|HIGH_REG~284 counter24:HOUR_CONTROL|HIGH_REG[1] } "NODE_NAME" } } { "counter24.vhd" "" { Text "F:/clock/counter24.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.988 ns ( 52.86 % ) " "Info: Total cell delay = 0.988 ns ( 52.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.881 ns ( 47.14 % ) " "Info: Total interconnect delay = 0.881 ns ( 47.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.869 ns" { counter24:HOUR_CONTROL|LOW_REG[2] counter24:HOUR_CONTROL|Equal0~26 counter24:HOUR_CONTROL|Add1~61 counter24:HOUR_CONTROL|Add1~64 counter24:HOUR_CONTROL|HIGH_REG~284 counter24:HOUR_CONTROL|HIGH_REG[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.869 ns" { counter24:HOUR_CONTROL|LOW_REG[2] counter24:HOUR_CONTROL|Equal0~26 counter24:HOUR_CONTROL|Add1~61 counter24:HOUR_CONTROL|Add1~64 counter24:HOUR_CONTROL|HIGH_REG~284 counter24:HOUR_CONTROL|HIGH_REG[1] } { 0.000ns 0.276ns 0.215ns 0.000ns 0.390ns 0.000ns } { 0.000ns 0.346ns 0.309ns 0.125ns 0.053ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK1HZ destination 4.142 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK1HZ\" to destination register is 4.142 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns CLK1HZ 1 CLK PIN_L3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_L3; Fanout = 1; CLK Node = 'CLK1HZ'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK1HZ } "NODE_NAME" } } { "top.vhd" "" { Text "F:/clock/top.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.556 ns) + CELL(0.053 ns) 1.473 ns adjuster:ADJUST_CONTROL\|CLK 2 COMB LCCOMB_X39_Y16_N8 1 " "Info: 2: + IC(0.556 ns) + CELL(0.053 ns) = 1.473 ns; Loc. = LCCOMB_X39_Y16_N8; Fanout = 1; COMB Node = 'adjuster:ADJUST_CONTROL\|CLK'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.609 ns" { CLK1HZ adjuster:ADJUST_CONTROL|CLK } "NODE_NAME" } } { "adjuster.vhd" "" { Text "F:/clock/adjuster.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.385 ns) + CELL(0.000 ns) 2.858 ns adjuster:ADJUST_CONTROL\|CLK~clkctrl 3 COMB CLKCTRL_G11 8 " "Info: 3: + IC(1.385 ns) + CELL(0.000 ns) = 2.858 ns; Loc. = CLKCTRL_G11; Fanout = 8; COMB Node = 'adjuster:ADJUST_CONTROL\|CLK~clkctrl'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.385 ns" { adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl } "NODE_NAME" } } { "adjuster.vhd" "" { Text "F:/clock/adjuster.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.666 ns) + CELL(0.618 ns) 4.142 ns counter24:HOUR_CONTROL\|HIGH_REG\[1\] 4 REG LCFF_X14_Y9_N23 10 " "Info: 4: + IC(0.666 ns) + CELL(0.618 ns) = 4.142 ns; Loc. = LCFF_X14_Y9_N23; Fanout = 10; REG Node = 'counter24:HOUR_CONTROL\|HIGH_REG\[1\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.284 ns" { adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|HIGH_REG[1] } "NODE_NAME" } } { "counter24.vhd" "" { Text "F:/clock/counter24.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.535 ns ( 37.06 % ) " "Info: Total cell delay = 1.535 ns ( 37.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.607 ns ( 62.94 % ) " "Info: Total interconnect delay = 2.607 ns ( 62.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.142 ns" { CLK1HZ adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|HIGH_REG[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.142 ns" { CLK1HZ CLK1HZ~combout adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|HIGH_REG[1] } { 0.000ns 0.000ns 0.556ns 1.385ns 0.666ns } { 0.000ns 0.864ns 0.053ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK1HZ source 4.142 ns - Longest register " "Info: - Longest clock path from clock \"CLK1HZ\" to source register is 4.142 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns CLK1HZ 1 CLK PIN_L3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_L3; Fanout = 1; CLK Node = 'CLK1HZ'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK1HZ } "NODE_NAME" } } { "top.vhd" "" { Text "F:/clock/top.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.556 ns) + CELL(0.053 ns) 1.473 ns adjuster:ADJUST_CONTROL\|CLK 2 COMB LCCOMB_X39_Y16_N8 1 " "Info: 2: + IC(0.556 ns) + CELL(0.053 ns) = 1.473 ns; Loc. = LCCOMB_X39_Y16_N8; Fanout = 1; COMB Node = 'adjuster:ADJUST_CONTROL\|CLK'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.609 ns" { CLK1HZ adjuster:ADJUST_CONTROL|CLK } "NODE_NAME" } } { "adjuster.vhd" "" { Text "F:/clock/adjuster.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.385 ns) + CELL(0.000 ns) 2.858 ns adjuster:ADJUST_CONTROL\|CLK~clkctrl 3 COMB CLKCTRL_G11 8 " "Info: 3: + IC(1.385 ns) + CELL(0.000 ns) = 2.858 ns; Loc. = CLKCTRL_G11; Fanout = 8; COMB Node = 'adjuster:ADJUST_CONTROL\|CLK~clkctrl'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.385 ns" { adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl } "NODE_NAME" } } { "adjuster.vhd" "" { Text "F:/clock/adjuster.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.666 ns) + CELL(0.618 ns) 4.142 ns counter24:HOUR_CONTROL\|LOW_REG\[2\] 4 REG LCFF_X14_Y9_N15 11 " "Info: 4: + IC(0.666 ns) + CELL(0.618 ns) = 4.142 ns; Loc. = LCFF_X14_Y9_N15; Fanout = 11; REG Node = 'counter24:HOUR_CONTROL\|LOW_REG\[2\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.284 ns" { adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|LOW_REG[2] } "NODE_NAME" } } { "counter24.vhd" "" { Text "F:/clock/counter24.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.535 ns ( 37.06 % ) " "Info: Total cell delay = 1.535 ns ( 37.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.607 ns ( 62.94 % ) " "Info: Total interconnect delay = 2.607 ns ( 62.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.142 ns" { CLK1HZ adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|LOW_REG[2] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.142 ns" { CLK1HZ CLK1HZ~combout adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|LOW_REG[2] } { 0.000ns 0.000ns 0.556ns 1.385ns 0.666ns } { 0.000ns 0.864ns 0.053ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.142 ns" { CLK1HZ adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|HIGH_REG[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.142 ns" { CLK1HZ CLK1HZ~combout adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|HIGH_REG[1] } { 0.000ns 0.000ns 0.556ns 1.385ns 0.666ns } { 0.000ns 0.864ns 0.053ns 0.000ns 0.618ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.142 ns" { CLK1HZ adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|LOW_REG[2] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.142 ns" { CLK1HZ CLK1HZ~combout adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|LOW_REG[2] } { 0.000ns 0.000ns 0.556ns 1.385ns 0.666ns } { 0.000ns 0.864ns 0.053ns 0.000ns 0.618ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "counter24.vhd" "" { Text "F:/clock/counter24.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "counter24.vhd" "" { Text "F:/clock/counter24.vhd" 37 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.869 ns" { counter24:HOUR_CONTROL|LOW_REG[2] counter24:HOUR_CONTROL|Equal0~26 counter24:HOUR_CONTROL|Add1~61 counter24:HOUR_CONTROL|Add1~64 counter24:HOUR_CONTROL|HIGH_REG~284 counter24:HOUR_CONTROL|HIGH_REG[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.869 ns" { counter24:HOUR_CONTROL|LOW_REG[2] counter24:HOUR_CONTROL|Equal0~26 counter24:HOUR_CONTROL|Add1~61 counter24:HOUR_CONTROL|Add1~64 counter24:HOUR_CONTROL|HIGH_REG~284 counter24:HOUR_CONTROL|HIGH_REG[1] } { 0.000ns 0.276ns 0.215ns 0.000ns 0.390ns 0.000ns } { 0.000ns 0.346ns 0.309ns 0.125ns 0.053ns 0.155ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.142 ns" { CLK1HZ adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|HIGH_REG[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.142 ns" { CLK1HZ CLK1HZ~combout adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|HIGH_REG[1] } { 0.000ns 0.000ns 0.556ns 1.385ns 0.666ns } { 0.000ns 0.864ns 0.053ns 0.000ns 0.618ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.142 ns" { CLK1HZ adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|LOW_REG[2] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.142 ns" { CLK1HZ CLK1HZ~combout adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|LOW_REG[2] } { 0.000ns 0.000ns 0.556ns 1.385ns 0.666ns } { 0.000ns 0.864ns 0.053ns 0.000ns 0.618ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}