adjuster.vhd

多功能计时器,具有校准

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY adjuster IS
    PORT(
         CLK1HZ : IN        STD_LOGIC;
         SET    : IN        STD_LOGIC;
        MODE   : IN        STD_LOGIC;
        EN      : IN       STD_LOGIC;
         S_ENOUT : IN      STD_LOGIC;
        M_ENOUT  : IN      STD_LOGIC;
        CLK      : OUT     STD_LOGIC;
        S_CE     : OUT     STD_LOGIC;
        M_CE     :OUT      STD_LOGIC;
        H_CE     : OUT     STD_LOGIC
);
END adjuster;

ARCHITECTURE rtl of adjuster IS
SIGNAL SEL    :STD_LOGIC;
SIGNAL SCE_REG    :STD_LOGIC;
SIGNAL MCE_REG    :STD_LOGIC;
SIGNAL HCE_REG    :STD_LOGIC;
SIGNAL CON        :integer RANGE 0 TO 3:=0;
BEGIN
COUNT: PROCESS(MODE,SEL)
BEGIN 
IF rising_edge(MODE) THEN
IF CON=3 THEN
CON<=0;
ELSE
CON<=CON+1;
END IF;
END IF;
END PROCESS;


CON_PRO:PROCESS(CON)
BEGIN
CASE CON IS
WHEN 0=>SEL<='1';
SCE_REG<='0';
MCE_REG<='0';
HCE_REG<='0';
WHEN 1=>SEL<='0';
SCE_REG<='1';
MCE_REG<='0';
HCE_REG<='0';
WHEN 2=>SEL<='0';
SCE_REG<='0';
MCE_REG<='1';
HCE_REG<='0';
WHEN 3=>SEL<='0';
SCE_REG<='0';
MCE_REG<='0';
HCE_REG<='1';
WHEN OTHERS=>SEL<='0';
SCE_REG<='0';
MCE_REG<='0';
HCE_REG<='0';

END CASE;
END PROCESS;

SEL_PRO:PROCESS(SEL)
BEGIN
CASE SEL IS
WHEN '0'=>S_CE<=SCE_REG;
          M_CE<=MCE_REG;
          H_CE<=HCE_REG;
          CLK<=SET;
WHEN '1'=>S_CE<=EN;
          M_CE<=S_ENOUT;
          H_CE<=M_ENOUT;
          CLK<=CLK1HZ;
WHEN OTHERS=>S_CE<=EN;
          M_CE<=S_ENOUT;
          H_CE<=M_ENOUT;
          CLK<=CLK1HZ;
END CASE;
END PROCESS;
END rtl;