📄 timer.tan.rpt
字号:
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[2] ; counter24:HOUR_CONTROL|HIGH_REG[3] ; SET ; SET ; None ; None ; 1.438 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[0] ; counter24:HOUR_CONTROL|HIGH_REG[1] ; SET ; SET ; None ; None ; 1.405 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[2] ; counter24:HOUR_CONTROL|HIGH_REG[2] ; SET ; SET ; None ; None ; 1.403 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[1] ; counter24:HOUR_CONTROL|HIGH_REG[1] ; SET ; SET ; None ; None ; 1.384 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[1] ; counter24:HOUR_CONTROL|LOW_REG[3] ; SET ; SET ; None ; None ; 1.327 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[1] ; counter24:HOUR_CONTROL|LOW_REG[2] ; SET ; SET ; None ; None ; 1.325 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[1] ; counter24:HOUR_CONTROL|LOW_REG[1] ; SET ; SET ; None ; None ; 1.323 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[3] ; counter24:HOUR_CONTROL|HIGH_REG[3] ; SET ; SET ; None ; None ; 1.307 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[2] ; counter24:HOUR_CONTROL|HIGH_REG[0] ; SET ; SET ; None ; None ; 1.305 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[3] ; counter24:HOUR_CONTROL|HIGH_REG[2] ; SET ; SET ; None ; None ; 1.272 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[2] ; counter24:HOUR_CONTROL|LOW_REG[3] ; SET ; SET ; None ; None ; 1.271 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[0] ; counter24:HOUR_CONTROL|HIGH_REG[3] ; SET ; SET ; None ; None ; 1.271 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[2] ; counter24:HOUR_CONTROL|LOW_REG[2] ; SET ; SET ; None ; None ; 1.269 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[2] ; counter24:HOUR_CONTROL|LOW_REG[1] ; SET ; SET ; None ; None ; 1.267 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[3] ; counter24:HOUR_CONTROL|HIGH_REG[1] ; SET ; SET ; None ; None ; 1.246 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[0] ; counter24:HOUR_CONTROL|HIGH_REG[2] ; SET ; SET ; None ; None ; 1.236 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[0] ; counter24:HOUR_CONTROL|LOW_REG[3] ; SET ; SET ; None ; None ; 1.189 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[0] ; counter24:HOUR_CONTROL|LOW_REG[2] ; SET ; SET ; None ; None ; 1.187 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[0] ; counter24:HOUR_CONTROL|LOW_REG[1] ; SET ; SET ; None ; None ; 1.185 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[3] ; counter24:HOUR_CONTROL|HIGH_REG[0] ; SET ; SET ; None ; None ; 1.174 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[1] ; counter24:HOUR_CONTROL|LOW_REG[3] ; SET ; SET ; None ; None ; 1.168 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[1] ; counter24:HOUR_CONTROL|LOW_REG[2] ; SET ; SET ; None ; None ; 1.166 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[1] ; counter24:HOUR_CONTROL|LOW_REG[1] ; SET ; SET ; None ; None ; 1.164 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[0] ; counter24:HOUR_CONTROL|HIGH_REG[0] ; SET ; SET ; None ; None ; 1.138 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[1] ; counter24:HOUR_CONTROL|HIGH_REG[3] ; SET ; SET ; None ; None ; 1.107 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[1] ; counter24:HOUR_CONTROL|HIGH_REG[2] ; SET ; SET ; None ; None ; 1.072 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[3] ; counter24:HOUR_CONTROL|LOW_REG[3] ; SET ; SET ; None ; None ; 1.030 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[3] ; counter24:HOUR_CONTROL|LOW_REG[2] ; SET ; SET ; None ; None ; 1.028 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[3] ; counter24:HOUR_CONTROL|LOW_REG[1] ; SET ; SET ; None ; None ; 1.026 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[1] ; counter24:HOUR_CONTROL|HIGH_REG[0] ; SET ; SET ; None ; None ; 0.974 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[1] ; counter24:HOUR_CONTROL|HIGH_REG[3] ; SET ; SET ; None ; None ; 0.885 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[1] ; counter24:HOUR_CONTROL|HIGH_REG[2] ; SET ; SET ; None ; None ; 0.850 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[0] ; counter24:HOUR_CONTROL|HIGH_REG[3] ; SET ; SET ; None ; None ; 0.750 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[0] ; counter24:HOUR_CONTROL|HIGH_REG[2] ; SET ; SET ; None ; None ; 0.715 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[2] ; counter24:HOUR_CONTROL|HIGH_REG[3] ; SET ; SET ; None ; None ; 0.680 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[0] ; counter24:HOUR_CONTROL|HIGH_REG[0] ; SET ; SET ; None ; None ; 0.609 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[3] ; counter24:HOUR_CONTROL|HIGH_REG[3] ; SET ; SET ; None ; None ; 0.609 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[2] ; counter24:HOUR_CONTROL|HIGH_REG[2] ; SET ; SET ; None ; None ; 0.609 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[0] ; counter24:HOUR_CONTROL|LOW_REG[0] ; SET ; SET ; None ; None ; 0.488 ns ;
+-------+------------------------------------------------+------------------------------------+------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Hold: 'MODE' ;
+------------------------------------------+--------------------------------+------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+------------------------------------------+--------------------------------+------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Not operational: Clock Skew > Data Delay ; adjuster:ADJUST_CONTROL|CON[1] ; counter24:HOUR_CONTROL|LOW_REG[0] ; MODE ; MODE ; None ; None ; 3.049 ns ;
; Not operational: Clock Skew > Data Delay ; adjuster:ADJUST_CONTROL|CON[1] ; counter24:HOUR_CONTROL|LOW_REG[1] ; MODE ; MODE ; None ; None ; 3.049 ns ;
; Not operational: Clock Skew > Data Delay ; adjuster:ADJUST_CONTROL|CON[1] ; counter24:HOUR_CONTROL|LOW_REG[2] ; MODE ; MODE ; None ; None ; 3.049 ns ;
; Not operational: Clock Skew > Data Delay ; adjuster:ADJUST_CONTROL|CON[1] ; counter24:HOUR_CONTROL|LOW_REG[3] ; MODE ; MODE ; None ; None ; 3.049 ns ;
; Not operational: Clock Skew > Data Delay ; adjuster:ADJUST_CONTROL|CON[1] ; counter24:HOUR_CONTROL|HIGH_REG[0] ; MODE ; MODE ; None ; None ; 3.049 ns ;
; Not operational: Clock Skew > Data Delay ; adjuster:ADJUST_CONTROL|CON[1] ; counter24:HOUR_CONTROL|HIGH_REG[1] ; MODE ; MODE ; None ; None ; 3.049 ns ;
; Not operational: Clock Skew > Data Delay ; adjuster:ADJUST_CONTROL|CON[1] ; counter24:HOUR_CONTROL|HIGH_REG[3] ; MODE ; MODE ; None ; None ; 3.049 ns ;
; Not operational: Clock Skew > Data Delay ; adjuster:ADJUST_CONTROL|CON[1] ; counter24:HOUR_CONTROL|HIGH_REG[2] ; MODE ; MODE ; None ; None ; 3.049 ns ;
; Not operational: Clock Skew > Data Delay ; adjuster:ADJUST_CONTROL|CON[0] ; counter24:HOUR_CONTROL|LOW_REG[0] ; MODE ; MODE ; None ; None ; 3.155 ns ;
; Not operational: Clock Skew > Data Delay ; adjuster:ADJUST_CONTROL|CON[0] ; counter24:HOUR_CONTROL|LOW_REG[1] ; MODE ; MODE ; None ; None ; 3.155 ns ;
; Not operational: Clock Skew > Data Delay ; adjuster:ADJUST_CONTROL|CON[0] ; counter24:HOUR_CONTROL|LOW_REG[2] ; MODE ; MODE ; None ; None ; 3.155 ns ;
; Not operational: Clock Skew > Data Delay ; adjuster:ADJUST_CONTROL|CON[0] ; counter24:HOUR_CONTROL|LOW_REG[3] ; MODE ; MODE ; None ; None ; 3.155 ns ;
; Not operational: Clock Skew > Data Delay ; adjuster:ADJUST_CONTROL|CON[0] ; counter24:HOUR_CONTROL|HIGH_REG[0] ; MODE ; MODE ; None ; None ; 3.155 ns ;
; Not operational: Clock Skew > Data Delay ; adjuster:ADJUST_CONTROL|CON[0] ; counter24:HOUR_CONTROL|HIGH_REG[1] ; MODE ; MODE ; None ; None ; 3.155 ns ;
; Not operational: Clock Skew > Data Delay ; adjuster:ADJUST_CONTROL|CON[0] ; counter24:HOUR_CONTROL|HIGH_REG[3] ; MODE ; MODE ; None ; None ; 3.155 ns ;
; Not operational: Clock Skew > Data Delay ; adjuster:ADJUST_CONTROL|CON[0] ; counter24:HOUR_CONTROL|HIGH_REG[2] ; MODE ; MODE ; None ; None ; 3.155 ns ;
+------------------------------------------+--------------------------------+------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
+-----------------------------------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+------------------------------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+------------------------------------+---------+------------+
; N/A ; None ; 10.178 ns ; counter24:HOUR_CONTROL|LOW_REG[3] ; LED5[2] ; MODE ;
; N/A ; None ; 10.166 ns ; counter24:HOUR_CONTROL|LOW_REG[1] ; LED5[2] ; MODE ;
; N/A ; None ; 10.126 ns ; counter24:HOUR_CONTROL|LOW_REG[2] ; LED5[2] ; MODE ;
; N/A ; None ; 10.091 ns ; counter24:HOUR_CONTROL|LOW_REG[0] ; LED5[5] ; MODE ;
; N/A ; None ; 9.995 ns ; counter24:HOUR_CONTROL|HIGH_REG[1] ; LED6[1] ; MODE ;
; N/A ; None ; 9.984 ns ; counter24:HOUR_CONTROL|LOW_REG[0] ; LED5[3] ; MODE ;
; N/A ; None ; 9.978 ns ; counter24:HOUR_CONTROL|LOW_REG[0] ; LED5[2] ; MODE ;
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