📄 timer.tan.rpt
字号:
; N/A ; 447.43 MHz ( period = 2.235 ns ) ; counter24:HOUR_CONTROL|LOW_REG[2] ; counter24:HOUR_CONTROL|HIGH_REG[1] ; MODE ; MODE ; None ; None ; 1.869 ns ;
; N/A ; 450.05 MHz ( period = 2.222 ns ) ; counter24:HOUR_CONTROL|LOW_REG[0] ; counter24:HOUR_CONTROL|HIGH_REG[1] ; MODE ; MODE ; None ; None ; 1.856 ns ;
; N/A ; 474.16 MHz ( period = 2.109 ns ) ; counter24:HOUR_CONTROL|LOW_REG[3] ; counter24:HOUR_CONTROL|HIGH_REG[1] ; MODE ; MODE ; None ; None ; 1.743 ns ;
; N/A ; 498.50 MHz ( period = 2.006 ns ) ; counter24:HOUR_CONTROL|LOW_REG[0] ; counter24:HOUR_CONTROL|LOW_REG[3] ; MODE ; MODE ; None ; None ; 1.640 ns ;
; N/A ; 499.00 MHz ( period = 2.004 ns ) ; counter24:HOUR_CONTROL|LOW_REG[0] ; counter24:HOUR_CONTROL|LOW_REG[2] ; MODE ; MODE ; None ; None ; 1.638 ns ;
; N/A ; 499.50 MHz ( period = 2.002 ns ) ; counter24:HOUR_CONTROL|LOW_REG[0] ; counter24:HOUR_CONTROL|LOW_REG[1] ; MODE ; MODE ; None ; None ; 1.636 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[2] ; counter24:HOUR_CONTROL|LOW_REG[3] ; MODE ; MODE ; None ; None ; 1.610 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[2] ; counter24:HOUR_CONTROL|LOW_REG[2] ; MODE ; MODE ; None ; None ; 1.608 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[2] ; counter24:HOUR_CONTROL|LOW_REG[1] ; MODE ; MODE ; None ; None ; 1.606 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[1] ; counter24:HOUR_CONTROL|HIGH_REG[1] ; MODE ; MODE ; None ; None ; 1.543 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[3] ; counter24:HOUR_CONTROL|LOW_REG[3] ; MODE ; MODE ; None ; None ; 1.527 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[3] ; counter24:HOUR_CONTROL|LOW_REG[2] ; MODE ; MODE ; None ; None ; 1.525 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[3] ; counter24:HOUR_CONTROL|LOW_REG[1] ; MODE ; MODE ; None ; None ; 1.523 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[2] ; counter24:HOUR_CONTROL|HIGH_REG[1] ; MODE ; MODE ; None ; None ; 1.487 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[2] ; counter24:HOUR_CONTROL|HIGH_REG[3] ; MODE ; MODE ; None ; None ; 1.438 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[0] ; counter24:HOUR_CONTROL|HIGH_REG[1] ; MODE ; MODE ; None ; None ; 1.405 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[2] ; counter24:HOUR_CONTROL|HIGH_REG[2] ; MODE ; MODE ; None ; None ; 1.403 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[1] ; counter24:HOUR_CONTROL|HIGH_REG[1] ; MODE ; MODE ; None ; None ; 1.384 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[1] ; counter24:HOUR_CONTROL|LOW_REG[3] ; MODE ; MODE ; None ; None ; 1.327 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[1] ; counter24:HOUR_CONTROL|LOW_REG[2] ; MODE ; MODE ; None ; None ; 1.325 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[1] ; counter24:HOUR_CONTROL|LOW_REG[1] ; MODE ; MODE ; None ; None ; 1.323 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[3] ; counter24:HOUR_CONTROL|HIGH_REG[3] ; MODE ; MODE ; None ; None ; 1.307 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[2] ; counter24:HOUR_CONTROL|HIGH_REG[0] ; MODE ; MODE ; None ; None ; 1.305 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[3] ; counter24:HOUR_CONTROL|HIGH_REG[2] ; MODE ; MODE ; None ; None ; 1.272 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[2] ; counter24:HOUR_CONTROL|LOW_REG[3] ; MODE ; MODE ; None ; None ; 1.271 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[0] ; counter24:HOUR_CONTROL|HIGH_REG[3] ; MODE ; MODE ; None ; None ; 1.271 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[2] ; counter24:HOUR_CONTROL|LOW_REG[2] ; MODE ; MODE ; None ; None ; 1.269 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[2] ; counter24:HOUR_CONTROL|LOW_REG[1] ; MODE ; MODE ; None ; None ; 1.267 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[3] ; counter24:HOUR_CONTROL|HIGH_REG[1] ; MODE ; MODE ; None ; None ; 1.246 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[0] ; counter24:HOUR_CONTROL|HIGH_REG[2] ; MODE ; MODE ; None ; None ; 1.236 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[0] ; counter24:HOUR_CONTROL|LOW_REG[3] ; MODE ; MODE ; None ; None ; 1.189 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[0] ; counter24:HOUR_CONTROL|LOW_REG[2] ; MODE ; MODE ; None ; None ; 1.187 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[0] ; counter24:HOUR_CONTROL|LOW_REG[1] ; MODE ; MODE ; None ; None ; 1.185 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[3] ; counter24:HOUR_CONTROL|HIGH_REG[0] ; MODE ; MODE ; None ; None ; 1.174 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[1] ; counter24:HOUR_CONTROL|LOW_REG[3] ; MODE ; MODE ; None ; None ; 1.168 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[1] ; counter24:HOUR_CONTROL|LOW_REG[2] ; MODE ; MODE ; None ; None ; 1.166 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[1] ; counter24:HOUR_CONTROL|LOW_REG[1] ; MODE ; MODE ; None ; None ; 1.164 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[0] ; counter24:HOUR_CONTROL|HIGH_REG[0] ; MODE ; MODE ; None ; None ; 1.138 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[1] ; counter24:HOUR_CONTROL|HIGH_REG[3] ; MODE ; MODE ; None ; None ; 1.107 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[1] ; counter24:HOUR_CONTROL|HIGH_REG[2] ; MODE ; MODE ; None ; None ; 1.072 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[3] ; counter24:HOUR_CONTROL|LOW_REG[3] ; MODE ; MODE ; None ; None ; 1.030 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[3] ; counter24:HOUR_CONTROL|LOW_REG[2] ; MODE ; MODE ; None ; None ; 1.028 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[3] ; counter24:HOUR_CONTROL|LOW_REG[1] ; MODE ; MODE ; None ; None ; 1.026 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[1] ; counter24:HOUR_CONTROL|HIGH_REG[0] ; MODE ; MODE ; None ; None ; 0.974 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[1] ; counter24:HOUR_CONTROL|HIGH_REG[3] ; MODE ; MODE ; None ; None ; 0.885 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[1] ; counter24:HOUR_CONTROL|HIGH_REG[2] ; MODE ; MODE ; None ; None ; 0.850 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[0] ; counter24:HOUR_CONTROL|HIGH_REG[3] ; MODE ; MODE ; None ; None ; 0.750 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[0] ; counter24:HOUR_CONTROL|HIGH_REG[2] ; MODE ; MODE ; None ; None ; 0.715 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[2] ; counter24:HOUR_CONTROL|HIGH_REG[3] ; MODE ; MODE ; None ; None ; 0.680 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[0] ; counter24:HOUR_CONTROL|HIGH_REG[0] ; MODE ; MODE ; None ; None ; 0.609 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[3] ; counter24:HOUR_CONTROL|HIGH_REG[3] ; MODE ; MODE ; None ; None ; 0.609 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[2] ; counter24:HOUR_CONTROL|HIGH_REG[2] ; MODE ; MODE ; None ; None ; 0.609 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[0] ; counter24:HOUR_CONTROL|LOW_REG[0] ; MODE ; MODE ; None ; None ; 0.488 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; adjuster:ADJUST_CONTROL|CON[0] ; adjuster:ADJUST_CONTROL|CON[1] ; MODE ; MODE ; None ; None ; 0.577 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; adjuster:ADJUST_CONTROL|CON[0] ; adjuster:ADJUST_CONTROL|CON[0] ; MODE ; MODE ; None ; None ; 0.488 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; adjuster:ADJUST_CONTROL|CON[1] ; adjuster:ADJUST_CONTROL|CON[1] ; MODE ; MODE ; None ; None ; 0.488 ns ;
+-------+------------------------------------------------+------------------------------------+------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'SET' ;
+-------+------------------------------------------------+------------------------------------+------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+------------------------------------+------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 487.09 MHz ( period = 2.053 ns ) ; counter24:HOUR_CONTROL|LOW_REG[2] ; counter24:HOUR_CONTROL|HIGH_REG[1] ; SET ; SET ; None ; None ; 1.869 ns ;
; N/A ; 490.20 MHz ( period = 2.040 ns ) ; counter24:HOUR_CONTROL|LOW_REG[0] ; counter24:HOUR_CONTROL|HIGH_REG[1] ; SET ; SET ; None ; None ; 1.856 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[3] ; counter24:HOUR_CONTROL|HIGH_REG[1] ; SET ; SET ; None ; None ; 1.743 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[0] ; counter24:HOUR_CONTROL|LOW_REG[3] ; SET ; SET ; None ; None ; 1.640 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[0] ; counter24:HOUR_CONTROL|LOW_REG[2] ; SET ; SET ; None ; None ; 1.638 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[0] ; counter24:HOUR_CONTROL|LOW_REG[1] ; SET ; SET ; None ; None ; 1.636 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[2] ; counter24:HOUR_CONTROL|LOW_REG[3] ; SET ; SET ; None ; None ; 1.610 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[2] ; counter24:HOUR_CONTROL|LOW_REG[2] ; SET ; SET ; None ; None ; 1.608 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[2] ; counter24:HOUR_CONTROL|LOW_REG[1] ; SET ; SET ; None ; None ; 1.606 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[1] ; counter24:HOUR_CONTROL|HIGH_REG[1] ; SET ; SET ; None ; None ; 1.543 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[3] ; counter24:HOUR_CONTROL|LOW_REG[3] ; SET ; SET ; None ; None ; 1.527 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[3] ; counter24:HOUR_CONTROL|LOW_REG[2] ; SET ; SET ; None ; None ; 1.525 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|LOW_REG[3] ; counter24:HOUR_CONTROL|LOW_REG[1] ; SET ; SET ; None ; None ; 1.523 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; counter24:HOUR_CONTROL|HIGH_REG[2] ; counter24:HOUR_CONTROL|HIGH_REG[1] ; SET ; SET ; None ; None ; 1.487 ns ;
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