timer.map.rpt

多功能计时器,具有校准

; Total combinational functions                 ; 31                                ;
; Combinational ALUT usage by number of inputs  ;                                   ;
;     -- 7 input functions                      ; 0                                 ;
;     -- 6 input functions                      ; 0                                 ;
;     -- 5 input functions                      ; 2                                 ;
;     -- 4 input functions                      ; 18                                ;
;     -- <=3 input functions                    ; 11                                ;
;                                               ;                                   ;
; Combinational ALUTs by mode                   ;                                   ;
;     -- normal mode                            ; 27                                ;
;     -- extended LUT mode                      ; 0                                 ;
;     -- arithmetic mode                        ; 4                                 ;
;     -- shared arithmetic mode                 ; 0                                 ;
;                                               ;                                   ;
; Estimated ALUT/register pairs used            ; 33                                ;
;                                               ;                                   ;
; Total registers                               ; 10                                ;
;     -- Dedicated logic registers              ; 10                                ;
;     -- I/O registers                          ; 0                                 ;
;                                               ;                                   ;
; Estimated ALMs:  partially or completely used ; 17                                ;
;                                               ;                                   ;
; I/O pins                                      ; 45                                ;
; Maximum fan-out node                          ; counter24:HOUR_CONTROL|LOW_REG[0] ;
; Maximum fan-out                               ; 13                                ;
; Total fan-out                                 ; 145                               ;
; Average fan-out                               ; 1.69                              ;
+-----------------------------------------------+-----------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                        ;
+------------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+--------------------------------+--------------+
; Compilation Hierarchy Node   ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name            ; Library Name ;
+------------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+--------------------------------+--------------+
; |timer                       ; 31 (0)            ; 10 (0)       ; 0                 ; 0            ; 0       ; 0         ; 0         ; 45   ; 0            ; |timer                         ; work         ;
;    |adjuster:ADJUST_CONTROL| ; 5 (5)             ; 2 (2)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |timer|adjuster:ADJUST_CONTROL ; work         ;
;    |counter24:HOUR_CONTROL|  ; 12 (12)           ; 8 (8)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |timer|counter24:HOUR_CONTROL  ; work         ;
;    |display:DIS_LED5|        ; 7 (7)             ; 0 (0)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |timer|display:DIS_LED5        ; work         ;
;    |display:DIS_LED6|        ; 7 (7)             ; 0 (0)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |timer|display:DIS_LED6        ; work         ;
+------------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+--------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 10    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 8     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Sat Sep 27 19:31:31 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off timer -c timer
Info: Found 2 design units, including 1 entities, in source file top.vhd
    Info: Found design unit 1: timer-rtl
    Info: Found entity 1: timer
Info: Found 2 design units, including 1 entities, in source file counter60.vhd
    Info: Found design unit 1: counter60-rtl
    Info: Found entity 1: counter60
Info: Found 2 design units, including 1 entities, in source file counter24.vhd
    Info: Found design unit 1: counter24-rtl
    Info: Found entity 1: counter24
Info: Found 2 design units, including 1 entities, in source file adjuster.vhd
    Info: Found design unit 1: adjuster-rtl
    Info: Found entity 1: adjuster
Info: Found 2 design units, including 1 entities, in source file display.vhd
    Info: Found design unit 1: display-rtl
    Info: Found entity 1: display
Info: Elaborating entity "timer" for the top level hierarchy
Info: Elaborating entity "adjuster" for hierarchy "adjuster:ADJUST_CONTROL"
Warning (10492): VHDL Process Statement warning at adjuster.vhd(70): signal "SCE_REG" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at adjuster.vhd(71): signal "MCE_REG" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at adjuster.vhd(72): signal "HCE_REG" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at adjuster.vhd(73): signal "SET" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at adjuster.vhd(74): signal "EN" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at adjuster.vhd(75): signal "S_ENOUT" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at adjuster.vhd(76): signal "M_ENOUT" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at adjuster.vhd(77): signal "CLK1HZ" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at adjuster.vhd(78): signal "EN" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at adjuster.vhd(79): signal "S_ENOUT" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at adjuster.vhd(80): signal "M_ENOUT" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at adjuster.vhd(81): signal "CLK1HZ" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info: Elaborating entity "counter60" for hierarchy "counter60:SEC_CONTROL"
Warning (10540): VHDL Signal Declaration warning at counter60.vhd(17): used explicit default value for signal "LOW_REG" because signal was never assigned a value
Warning (10034): Output port "LOW[3]" at counter60.vhd(11) has no driver
Warning (10034): Output port "LOW[2]" at counter60.vhd(11) has no driver
Warning (10034): Output port "LOW[1]" at counter60.vhd(11) has no driver
Warning (10034): Output port "LOW[0]" at counter60.vhd(11) has no driver
Info: Elaborating entity "counter24" for hierarchy "counter24:HOUR_CONTROL"
Info: Elaborating entity "display" for hierarchy "display:DIS_LED1"
Info: Clock multiplexers have been protected
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "LED1[0]" stuck at VCC
    Warning: Pin "LED1[1]" stuck at VCC
    Warning: Pin "LED1[2]" stuck at VCC
    Warning: Pin "LED1[3]" stuck at VCC
    Warning: Pin "LED1[4]" stuck at VCC
    Warning: Pin "LED1[5]" stuck at VCC
    Warning: Pin "LED1[6]" stuck at GND
    Warning: Pin "LED2[0]" stuck at VCC
    Warning: Pin "LED2[1]" stuck at VCC
    Warning: Pin "LED2[2]" stuck at VCC
    Warning: Pin "LED2[3]" stuck at VCC
    Warning: Pin "LED2[4]" stuck at VCC
    Warning: Pin "LED2[5]" stuck at VCC
    Warning: Pin "LED2[6]" stuck at GND
    Warning: Pin "LED3[0]" stuck at VCC
    Warning: Pin "LED3[1]" stuck at VCC
    Warning: Pin "LED3[2]" stuck at VCC
    Warning: Pin "LED3[3]" stuck at VCC
    Warning: Pin "LED3[4]" stuck at VCC
    Warning: Pin "LED3[5]" stuck at VCC
    Warning: Pin "LED3[6]" stuck at GND
    Warning: Pin "LED4[0]" stuck at VCC
    Warning: Pin "LED4[1]" stuck at VCC
    Warning: Pin "LED4[2]" stuck at VCC
    Warning: Pin "LED4[3]" stuck at VCC
    Warning: Pin "LED4[4]" stuck at VCC
    Warning: Pin "LED4[5]" stuck at VCC
    Warning: Pin "LED4[6]" stuck at GND
Info: Implemented 76 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 42 output pins
    Info: Implemented 31 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 46 warnings
    Info: Allocated 157 megabytes of memory during processing
    Info: Processing ended: Sat Sep 27 19:31:34 2008
    Info: Elapsed time: 00:00:03