startup.s

一个简单实用的嵌入式操作系统,实现了嵌入式操作系统的基本模块：内存管理、系统调度 、系统调用等。

;/*
; *  boot/startup.s
; *
; *  Copyright (C) 2008/05/18 Wang Qiang
; *
; * This program is free software; you can redistribute it and/or modify
; * it under the terms of the GNU General Public License version 2 as
; * published by the Free Software Foundation.
; *
; * For sumsang, S3C2440 
; */

	
	INCLUDE asm\config.inc
	INCLUDE mcu\memregions.inc
	EXPORT reset
	EXPORT __user_initial_stackheap
	EXPORT __rt_div0
	IMPORT irq_handler
	IMPORT kmain
	IMPORT ||Load$$CODE$$Base||
	IMPORT ||Load$$DATA$$Base||
	IMPORT ||Image$$DATA$$Base||
	IMPORT ||Image$$DATA$$Length||
	IMPORT ||Image$$BSS$$ZI$$Base||
	IMPORT ||Image$$BSS$$ZI$$Length||
	
	AREA BOOT,CODE,READONLY
	ENTRY
	CODE32
    LDR     PC,     _reset
    LDR     PC,     _undef
    LDR     PC,     _swi
    LDR     PC,     _pref
    LDR     PC,     _abt
    DCD     0xb9205f80
    LDR     PC,     _irq
    LDR     PC,     _fiq
_reset      DCD     reset
_undef      DCD     undefined_instruction
_swi        DCD     swi_handler
_pref       DCD     prefetch_abort
_abt        DCD     data_abort
_irq        DCD     irq_handler
_fiq        DCD     fiq
	
reset	
    mov    r0, #0x0                 ; /* MMU mandatory */
    mcr    p15, 0, r0, c1, c0, 0    ; /* MMU init  */
    mcr    p15, 0, r0, c7, c7, 0    ; /* flush v3/v4 cache */
    mcr    p15, 0, r0, c8, c7, 0    ; /* flush v4 TLB mcr    p15, 0, r0,c15, c0, 0 Prefetch Disable*/

; Watchdog Setup ---------------------------------------------------------------

    IF      WT_SETUP != 0
    LDR     R0, =WT_BASE
    LDR     R1, =WTCON_Val
    LDR     R2, =WTDAT_Val
    STR     R2, [R0, #WTCNT_OFS]
    STR     R2, [R0, #WTDAT_OFS]
    STR     R1, [R0, #WTCON_OFS]
    ENDIF
    

; Clock Setup ------------------------------------------------------------------
    
    IF      (:LNOT:(:DEF:NO_CLOCK_SETUP)):LAND:(CLOCK_SETUP != 0)
    LDR     R0, =CLOCK_BASE
    LDR     R1,      =LOCKTIME_Val
    STR     R1, [R0, #LOCKTIME_OFS]
    MOV     R1,      #CLKDIVN_Val  
    STR     R1, [R0, #CLKDIVN_OFS]
    LDR     R1,      =CAMDIVN_Val
    STR     R1, [R0, #CAMDIVN_OFS]
    LDR     R1,      =MPLLCON_Val
    STR     R1, [R0, #MPLLCON_OFS]
    LDR     R1,      =UPLLCON_Val
    STR     R1, [R0, #UPLLCON_OFS]
    MOV     R1,      #CLKSLOW_Val
    STR     R1, [R0, #CLKSLOW_OFS]
    LDR     R1,      =CLKCON_Val
    STR     R1, [R0, #CLKCON_OFS]
    ENDIF


; Memory Controller Setup ------------------------------------------------------

    IF      (:LNOT:(:DEF:NO_MC_SETUP)):LAND:(CLOCK_SETUP != 0)
    LDR     R0, =MC_BASE
    LDR     R1,      =BWSCON_Val
    STR     R1, [R0, #BWSCON_OFS]
    LDR     R1,      =BANKCON0_Val
    STR     R1, [R0, #BANKCON0_OFS]
    LDR     R1,      =BANKCON1_Val
    STR     R1, [R0, #BANKCON1_OFS]
    LDR     R1,      =BANKCON2_Val
    STR     R1, [R0, #BANKCON2_OFS]
    LDR     R1,      =BANKCON3_Val
    STR     R1, [R0, #BANKCON3_OFS]
    LDR     R1,      =BANKCON4_Val
    STR     R1, [R0, #BANKCON4_OFS]
    LDR     R1,      =BANKCON5_Val
    STR     R1, [R0, #BANKCON5_OFS]
    LDR     R1,      =BANKCON6_Val
    STR     R1, [R0, #BANKCON6_OFS]
    LDR     R1,      =BANKCON7_Val
    STR     R1, [R0, #BANKCON7_OFS]
    LDR     R1,      =REFRESH_Val
    STR     R1, [R0, #REFRESH_OFS]
    MOV     R1,      #BANKSIZE_Val
    STR     R1, [R0, #BANKSIZE_OFS]
    MOV     R1,      #MRSRB6_Val
    STR     R1, [R0, #MRSRB6_OFS]
    MOV     R1,      #MRSRB7_Val
    STR     R1, [R0, #MRSRB7_OFS]
    ENDIF          	              

                   
; I/O Pins Setup ---------------------------------------------------------------
              
    IF      (:LNOT:(:DEF:NO_GP_SETUP)):LAND:(GP_SETUP != 0)

    IF      GPA_SETUP != 0
    LDR     R0, =GPA_BASE
    LDR     R1, =GPACON_Val
    STR     R1, [R0, #GPCON_OFS]
    ENDIF

    IF      GPB_SETUP != 0
    LDR     R0, =GPB_BASE
    LDR     R1, =GPBCON_Val
    STR     R1, [R0, #GPCON_OFS]
    LDR     R1, =GPBUP_Val
    STR     R1, [R0, #GPUP_OFS]
    ENDIF

    IF      GPC_SETUP != 0
    LDR     R0, =GPC_BASE
    LDR     R1, =GPCCON_Val
    STR     R1, [R0, #GPCON_OFS]
    LDR     R1, =GPCUP_Val
    STR     R1, [R0, #GPUP_OFS]
    ENDIF

    IF      GPD_SETUP != 0
    LDR     R0, =GPD_BASE
    LDR     R1, =GPDCON_Val
    STR     R1, [R0, #GPCON_OFS]
    LDR     R1, =GPDUP_Val
    STR     R1, [R0, #GPUP_OFS]
    ENDIF

    IF      GPE_SETUP != 0
    LDR     R0, =GPE_BASE
    LDR     R1, =GPECON_Val
    STR     R1, [R0, #GPCON_OFS]
    LDR     R1, =GPEUP_Val
    STR     R1, [R0, #GPUP_OFS]
    ENDIF

    IF      GPF_SETUP != 0
    LDR     R0, =GPF_BASE
    LDR     R1, =GPFCON_Val
    STR     R1, [R0, #GPCON_OFS]
    LDR     R1, =GPFUP_Val
    STR     R1, [R0, #GPUP_OFS]
    ENDIF

    IF      GPG_SETUP != 0
    LDR     R0, =GPG_BASE
    LDR     R1, =GPGCON_Val
    STR     R1, [R0, #GPCON_OFS]
    LDR     R1, =GPGUP_Val
    STR     R1, [R0, #GPUP_OFS]
    ENDIF
  
    IF      GPH_SETUP != 0
    LDR     R0, =GPH_BASE
    LDR     R1, =GPHCON_Val
    STR     R1, [R0, #GPCON_OFS]
    LDR     R1, =GPHUP_Val
    STR     R1, [R0, #GPUP_OFS]
    ENDIF

    IF      GPJ_SETUP != 0
    LDR     R0, =GPJ_BASE
    LDR     R1, =GPJCON_Val
    STR     R1, [R0, #GPCON_OFS]
    LDR     R1, =GPJUP_Val
    STR     R1, [R0, #GPUP_OFS]
    ENDIF
               
    ENDIF
    

; Copy Exception Vectors to Internal RAM ---------------------------------------
    IF      :DEF:RAM_INTVEC
    ADR     R8,  Vectors    ; Source
    LDR     R9, =IRAM_BASE  ; Destination
    LDMIA   R8!, {R0-R7}    ; Load Vectors 
    STMIA   R9!, {R0-R7}    ; Store Vectors 
    LDMIA   R8!, {R0-R7}    ; Load Handler Addresses 
    STMIA   R9!, {R0-R7}    ; Store Handler Addresses
    ENDIF

;//Setup Stack for each mode

	;// Enter Undefined Instruction Mode and set its Stack Pointer
    MSR     CPSR_c, #Mode_UND|I_Bit|F_Bit
    LDR		SP, =UND_Stack

	;// Enter Abort Mode and set its Stack Pointer
    MSR     CPSR_c, #Mode_ABT|I_Bit|F_Bit
    LDR		SP, =ABT_Stack

	;// Enter FIQ Mode and set its Stack Pointer
    MSR     CPSR_c, #Mode_FIQ|I_Bit|F_Bit
    LDR		SP, =FIQ_Stack

	;// Enter IRQ Mode and set its Stack Pointer
    MSR     CPSR_c, #Mode_IRQ|I_Bit|F_Bit
    LDR		SP, =IRQ_Stack

	;// Enter Supervisor Mode and set its Stack Pointer
    MSR     CPSR_c, #Mode_SVC|I_Bit|F_Bit
    LDR		SP, =SVC_Stack

	;// Enter SYS Mode and set its Stack Pointer(User Stack)
    MSR     CPSR_c, #Mode_SYS
    LDR		SP, =User_Stack
   ;//return to SVC mode
    MSR     CPSR_c, #Mode_SVC|I_Bit|F_Bit
    

    ldr R0, =||Load$$CODE$$Base||
    mov R1, #2
    ldr R2, =VEC_ADR
vectblcpy
    ldmia R0!,{R3-R10}
    stmia R2!,{R3-R10}
    subs R1, R1, #1
    bne vectblcpy

    ldr R0, =||Load$$DATA$$Base||
    ldr R1, =||Image$$DATA$$Base||
    ldr R2, =||Image$$DATA$$Length||
datacpy
    ldmia R0!,{R3-R10}
    stmia R1!,{R3-R10}
    subs R2, R2, #32
    bgt datacpy
    
    ldr R1, =||Image$$BSS$$ZI$$Base||
    ldr R2, =||Image$$BSS$$ZI$$Length||
    mov R3 , #0
    mov R4 , #0
    mov R5 , #0
    mov R6 , #0
    mov R7 , #0
    mov R8 , #0
    mov R9 , #0
    mov R10, #0
bssclr
    stmia R1!,{R3-R10}
    subs R2, R2, #32
    bgt bssclr

;// main entry of C
    B kmain
    B reset

undefined_instruction
    B reset
swi_handler
    B reset
prefetch_abort
    B reset
data_abort
    B reset
fiq
    B reset	
	
__user_initial_stackheap 
	LDR	  r0,=bottom_of_heap   
	MOV   pc,lr
    
__rt_div0
	B       __rt_div0

	AREA    Myheap, DATA, NOINIT, ALIGN=2
bottom_of_heap     SPACE   256  

	END