📄 ask.mdl
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Model {
Name "ask"
Version 3.00
SimParamPage "Solver"
SampleTimeColors off
InvariantConstants off
WideVectorLines off
ShowLineWidths off
ShowPortDataTypes off
StartTime "0.0"
StopTime "100"
SolverMode "Auto"
Solver "ode45"
RelTol "1e-3"
AbsTol "auto"
Refine "1"
MaxStep "auto"
InitialStep "auto"
FixedStep "auto"
MaxOrder 5
OutputOption "RefineOutputTimes"
OutputTimes "[]"
LoadExternalInput off
ExternalInput "[t, u]"
SaveTime on
TimeSaveName "tout"
SaveState off
StateSaveName "xout"
SaveOutput on
OutputSaveName "yout"
LoadInitialState off
InitialState "xInitial"
SaveFinalState off
FinalStateName "xFinal"
SaveFormat "Matrix"
LimitMaxRows off
MaxRows "1000"
Decimation "1"
AlgebraicLoopMsg "warning"
MinStepSizeMsg "warning"
UnconnectedInputMsg "warning"
UnconnectedOutputMsg "warning"
UnconnectedLineMsg "warning"
InheritedTsInSrcMsg "warning"
IntegerOverflowMsg "warning"
UnnecessaryDatatypeConvMsg "none"
Int32ToFloatConvMsg "warning"
SignalLabelMismatchMsg "none"
ConsistencyChecking "off"
ZeroCross on
SimulationMode "normal"
BlockDataTips on
BlockParametersDataTip on
BlockAttributesDataTip off
BlockPortWidthsDataTip off
BlockDescriptionStringDataTip off
BlockMaskParametersDataTip off
ToolBar on
StatusBar on
BrowserShowLibraryLinks off
BrowserLookUnderMasks off
OptimizeBlockIOStorage on
BufferReuse on
BooleanDataType off
RTWSystemTargetFile "grt.tlc"
RTWInlineParameters off
RTWRetainRTWFile off
RTWTemplateMakefile "grt_default_tmf"
RTWMakeCommand "make_rtw"
RTWGenerateCodeOnly off
ExtModeMexFile "ext_comm"
ExtModeBatchMode off
ExtModeTrigType "manual"
ExtModeTrigMode "oneshot"
ExtModeTrigPort "1"
ExtModeTrigElement "any"
ExtModeTrigDuration 1000
ExtModeTrigHoldOff 0
ExtModeTrigDelay 0
ExtModeTrigDirection "rising"
ExtModeTrigLevel 0
ExtModeArchiveMode "off"
ExtModeAutoIncOneShot off
ExtModeIncDirWhenArm off
ExtModeAddSuffixToVar off
ExtModeWriteAllDataToWs off
ExtModeArmWhenConnect off
Created "Tue Nov 16 13:21:29 1999"
UpdateHistory "UpdateHistoryNever"
ModifiedByFormat "%<Auto>"
ModifiedDateFormat "%<Auto>"
LastModifiedDate "Sun Dec 12 17:42:25 1999"
ModelVersionFormat "1.%<AutoIncrement:10>"
ConfigurationManager "none"
BlockDefaults {
Orientation "right"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "ask"
Location [348, 75, 848, 376]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "automatic"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
AutoZoom on
ReportName "simulink-default.rpt"
Block {
BlockType Display
Name "Bit Error Details"
Ports [1, 0, 0, 0, 0]
Position [400, 70, 490, 150]
Format "short"
Decimation "1"
Floating off
SampleTime "-1"
}
Block {
BlockType SignalGenerator
Name "Digital signal \nsource"
Position [20, 130, 50, 160]
WaveForm "square"
Amplitude "1"
Frequency "2500"
Units "Hertz"
}
Block {
BlockType Reference
Name "Error Rate Calculation1"
Ports [2, 1, 0, 0, 0]
Position [295, 88, 375, 132]
SourceBlock "commsink/Error Rate Calculation"
SourceType "Error Rate Calculation"
Ts "td"
N "1"
PMode "Port"
WsName "ErrorVec"
RsMode2 off
}
Block {
BlockType Saturate
Name "Limiter"
Position [240, 105, 270, 135]
UpperLimit "1"
LowerLimit "-1"
}
Block {
BlockType Reference
Name "Master Clock frequency fs"
Ports [0, 1, 0, 0, 0]
Position [110, 16, 150, 44]
SourceBlock "simulink_extras/Flip Flops/Clock"
SourceType "Digital clock"
MaskParam1 "2"
}
Block {
BlockType Reference
Name "Noise \nGenerator"
Ports [0, 1, 0, 0, 0]
Position [15, 60, 45, 90]
SourceBlock "simulink3/Sources/Band-Limited\nWhite Noise"
SourceType "Continuous White Noise."
Cov "[0.1]"
Ts "0.1"
seed "[1345319]"
}
Block {
BlockType Reference
Name "Sample\nand Hold"
Ports [1, 1, 0, 1, 0]
Position [165, 99, 215, 141]
SourceBlock "dspswit2/Sample\nand Hold"
SourceType "Sample and Hold"
trig "Rising edge"
initCond "0"
}
Block {
BlockType Scope
Name "Scope"
Ports [1, 0, 0, 0, 0]
Position [425, 194, 455, 226]
Floating off
Location [457, 450, 781, 689]
Open off
NumInputPorts "1"
TickLabels "OneTimeTick"
ZoomMode "on"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
Grid "on"
TimeRange "auto"
YMin "-5"
YMax "1000"
SaveToWorkspace off
SaveName "ScopeData"
DataFormat "StructureWithTime"
LimitMaxRows on
MaxRows "5000"
Decimation "1"
SampleInput off
SampleTime "0"
}
Block {
BlockType Sum
Name "Sum4"
Ports [2, 1, 0, 0, 0]
Position [100, 110, 120, 130]
ShowName off
IconShape "round"
Inputs "++"
SaturateOnIntegerOverflow on
Port {
PortNumber 1
Name "Summer"
TestPoint off
RTWStorageClass "Auto"
}
}
Line {
SrcBlock "Sample\nand Hold"
SrcPort 1
DstBlock "Limiter"
DstPort 1
}
Line {
Labels [2, 0]
SrcBlock "Noise \nGenerator"
SrcPort 1
Points [0, 20]
DstBlock "Sum4"
DstPort 1
}
Line {
Name "Summer"
Labels [0, 0]
SrcBlock "Sum4"
SrcPort 1
DstBlock "Sample\nand Hold"
DstPort 1
}
Line {
SrcBlock "Master Clock frequency fs"
SrcPort 1
Points [35, 0]
DstBlock "Sample\nand Hold"
DstPort trigger
}
Line {
SrcBlock "Limiter"
SrcPort 1
DstBlock "Error Rate Calculation1"
DstPort 2
}
Line {
SrcBlock "Digital signal \nsource"
SrcPort 1
Points [5, 0]
Branch {
DstBlock "Sum4"
DstPort 2
}
Branch {
Points [0, 45; 220, 0]
DstBlock "Error Rate Calculation1"
DstPort 1
}
}
Line {
SrcBlock "Error Rate Calculation1"
SrcPort 1
Points [5, 0]
Branch {
DstBlock "Bit Error Details"
DstPort 1
}
Branch {
Points [0, 100]
DstBlock "Scope"
DstPort 1
}
}
}
}
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