slfprgr-trim-qc.asm

M68HC08 及HCS08系列单片机bootloader引导程序源码、示例

;*********************************************************************
; HEADER_START
;
;  	   $File Name: slfprgR-trim-qc.asm$
;      Project:        Developper's HC08 Bootloader Slave
;      Description:    QB main bootloader file
;      Platform:       HC08
;      $Version: 6.0.7.0$
;      $Date: Sep-3-2007$ 
;      $Last Modified By: r30323$
;      Company:        Freescale Semiconductor
;      Security:       General Business
;
; =================================================================== 
; Copyright (c):      Freescale Semiconductor, 2004, All rights reserved.
;
; =================================================================== 
; THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY
; EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
; PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL FREESCALE OR
; ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
; NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
; HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
; STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
; OF THE POSSIBILITY OF SUCH DAMAGE.
; ===================================================================
;
; HEADER_END


; Trim values differ by internal oscillator selection e.g.:
;
;    4MHz  = example trim 0x5B
;    8MHz  = example trim 0x61
; 12.8MHz  = example trim 0x5F
; 25.6MHz  = example trim 0x42
;

; external define HICLOCK (5V only, bus clock 6.4MHz), if not defined, 3.2MHz bus clock
; & trimming is used)

; external define LIN = uses single wire communication, RXD hears all TXD transmissions
; also "lazy" delay used

;
; FLBPR (Flash protection) feature is not used in QC16 bootloader since
; Flash between $B000 and $BFFF is always protected in case *any* protection
; is used. See  2.6.6 FLASH Block Protect Register  chapter of QC16 datasheet.
;

    include "reg-qc.h"

RCS_ENA         EQU     0     		; READ COMMAND SUPPORTED?

  IFNE RCS_ENA
RCS             EQU     $80   		; READ COMMAND SUPPORTED
  ELSE
RCS             EQU     0     		; READ COMMAND unSUPPORTED
  ENDIF

VER_NUM         EQU     1     		; FC protocol version number


ERBLK_LEN	  	EQU	    64
WRBLK_LEN	    EQU	    32

            IF SIZE = 8		      ; QC8
FLS_BEG		    EQU	    $DE00     ; specify memory limit!
            ENDIF

            IF SIZE = 16		    ; QC16
FLS_BEG		    EQU	    $BE00     ; specify memory limit!
            ENDIF

IDENTS          MACRO

                DC.B    'QC'    ; QC string

            IF SIZE = 8		      ; QC8
                DC.B    '8'   ; QC8 string
            ENDIF
            
            IF SIZE = 16		      ; QC16
                DC.B    '16'  ; QC16 string
            ENDIF
            

            IFDEF HICLOCK
                DC.B    '-hi'   ; hi clock string
            ENDIF

                DC.B    '-t',0

                ENDM
              
FLS_END		    EQU	    $FC80       ; this is APL_VECT address (also from PRM file)
INT_VECT	    EQU	    $FFD6


FLBPRMASK     EQU     $C000       ; this is CPU specific FLBPR mask (i.e. bits that are always in the address)

SPEED         EQU     8			; 4 x f(BUS)

ROMSTART      EQU     $2800

GETBYTE       EQU     ROMSTART
RDVRRNG       EQU     ROMSTART+3
ERARNGE       EQU     ROMSTART+6 
PRGRNGE       EQU     ROMSTART+9
DELNUS        EQU     ROMSTART+12

RAMSTART      EQU     $80
CTRLBYT       EQU     RAMSTART+$08
CPUSPD        EQU     RAMSTART+$09
LADDR         EQU     RAMSTART+$0A
DATA          EQU     RAMSTART+$0C

TXDDDR        EQU     DDRB
TXDPORT       EQU     PTB
TXDBIT        EQU     5
RXDPORT       EQU     PTB
RXDBIT        EQU     4

;*******************************************************************************************

    XDEF    FLBPR	; external define for FLBPR

    XDEF    main
    XDEF    VEC1
    XDEF    VEC2
    XDEF    APL_VECT		  ; 'API' address of private TRIM value
    XDEF    VEC4
    XDEF    VEC5
    XDEF    VEC6
    XDEF    VEC7
    XDEF    VEC8
    XDEF    VEC9
    XDEF    VEC10
    XDEF    VEC11
    XDEF    VEC12
    XDEF    VEC13
    XDEF    VEC14
    XDEF    VEC15
    XDEF    VEC16
    XDEF    VEC17
    XDEF    VEC18
    XDEF    VEC19
    XDEF    VEC20


WR_DATA     EQU     'W'
RD_DATA     EQU     'R'
ENDPRG      EQU     'Q'
ERASE       EQU     'E'
ACK         EQU     $FC
IDENT       EQU     'I'

T100MS      EQU     255

ILOP      MACRO
            DC.B    $32             ; this is illegal operation code
          ENDM
;*******************************************************************************************
MY_ZEROPAGE:	SECTION  SHORT

ADRS:	  DS.W	  1
LEN:	  DS.B	  1
STAT:	  DS.B	  1
STSRSR: DS.B    1               ; storage for SRSR reg.

DEFAULT_RAM:    SECTION

;*******************************************************************************************
APL_VECT_ROM:	SECTION

APL_VECT:
PRIV:    DC.B    $80,0,0,0,0,0,0,0 ; 8 bytes reserved for bootloader's private use
        
VEC0:   JMP     main            ; vector 0
VEC1:   JMP     main            ; vector 1
VEC2:   JMP     main            ; vector 2
VEC3:   JMP     main            ; vector 3
VEC4:   JMP     main            ; vector 4
VEC5:   JMP     main            ; vector 5
VEC6:   JMP     main            ; vector 6
VEC7:   JMP     main            ; vector 7
VEC8:   JMP     main            ; vector 8
VEC9:   JMP     main            ; vector 9
VEC10:  JMP     main            ; vector 10
VEC11:  JMP     main            ; vector 11
VEC12:  JMP     main            ; vector 12
VEC13:  JMP     main            ; vector 13
VEC14   JMP     main            ; vector 14
VEC15:  JMP     main            ; vector 15
VEC16:  JMP     main            ; vector 16
VEC17:  JMP     main            ; vector 17
VEC18:  JMP     main            ; vector 18
VEC19:  JMP     main            ; vector 19
VEC20:  JMP     main            ; vector 20

;*******************************************************************************************
FLB_PROT_ROM:	SECTION
      IF SIZE = 16		; QC16
FLBPR:  DC.B    $FF   ; FLASH protection DISABLED
      ELSE
FLBPR:  DC.B    (FLS_END+2*ERBLK_LEN-FLBPRMASK)/ERBLK_LEN ; FLASH protection block start - MUST CHANGE ACCORDING TO MEMORY MAPPING
      ENDIF
CODE_ROM:	SECTION 

ID_STRING1:
        DC.B    VER_NUM | RCS   ; version number & "Read command supported" flag
        DC.W    FLS_BEG         ; START ADDRESS OF FLASH    
        DC.W    FLS_END         ; END ADDRESS OF FLASH    
        DC.W    APL_VECT        ; POINTER TO APPLICATION VECTOR TABLE
        DC.W    INT_VECT        ; POINTER TO BEGINING OF FLASH INT. VECTORS
        DC.W    ERBLK_LEN       ; ERASE BLCK LENGTH OF FLASH ALG.
        DC.W    WRBLK_LEN       ; WRITE BLCK LENGTH OF FLASH ALG.
ID_STRING1_END:

ID_STRING2:
	    IDENTS
ID_STRING2_END:

;*******************************************************************************************
FL1_PROT_ROM:	SECTION
; 21 bytes
main:	
        LDA     SRSR            ;[3] fetch RESET status reg.
        STA     STSRSR          ;[2] store for later re-use
        TSTA                    ;[1] check if zero (this happens if RESET pulse is too short)

        BEQ     slfprg          ;[2] if so, jump to self programming                
        AND     #%10000000      ;[2] mask only POR RESET source      
        BNE     slfprg          ;[2] any of these sources, go to self programming

		    LDA     PRIV     				;[3] fetch private OSCTRIM