📄 prescale_counter_map.mrp
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Release 9.1i Map J.30Xilinx Mapping Report File for Design 'prescale_counter'Design Information------------------Command Line : D:\Xilinx91i\bin\nt\map.exe -ise
D:/ise_book/Example-5-1/Constraints_Demo/prescale_counter_ver/prescale_counter_v
er.ise -intstyle ise -p xc5vlx30t-ff665-3 -w -logic_opt off -ol high -t 1 -cm
area -k 6 -o prescale_counter_map.ncd prescale_counter.ngd prescale_counter.pcf Target Device : xc5vlx30tTarget Package : ff665Target Speed : -3Mapper Version : virtex5 -- $Revision: 1.36 $Mapped Date : Tue Dec 12 16:14:38 2006Design Summary--------------Number of errors: 0Number of warnings: 0Slice Logic Utilization: Number of Slice Registers: 32 out of 19,200 1% Number used as Flip Flops: 32 Number of Slice LUTs: 33 out of 19,200 1% Number used as logic: 32 out of 19,200 1% Number using O6 output only: 3 Number using O5 output only: 28 Number using O5 and O6: 1 Number used as exclusive route-thru: 1 Number of route-thrus: 29 out of 38,400 1% Number using O6 output only: 29Slice Logic Distribution: Number of occupied Slices: 10 out of 4,800 1% Number of LUT Flip Flop pairs used: 33 Number with an unused Flip Flop: 1 out of 33 3% Number with an unused LUT: 0 out of 33 0% Number of fully used LUT-FF pairs: 32 out of 33 96% A LUT Flip Flop pair for this architecture represents one LUT paired with one Flip Flop within a slice. The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails.IO Utilization: Number of bonded IOBs: 34 out of 402 8%Specific Feature Utilization: Number of BUFG/BUFGCTRLs: 1 out of 32 3% Number used as BUFGs: 1Total equivalent gate count for design: 476Additional JTAG gate count for IOBs: 1,632Peak Memory Usage: 353 MBTotal REAL time to MAP completion: 1 mins 54 secs Total CPU time to MAP completion: 1 mins 37 secs Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group and Partition SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 12 - Configuration String InformationSection 1 - Errors------------------Section 2 - Warnings--------------------Section 3 - Informational-------------------------INFO:MapLib:562 - No environment variables are currently set.INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs in the
schematic.INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
0.000 to 85.000 Celsius)INFO:Pack:1720 - Initializing voltage to 0.950 Volts. (default - Range: 0.950 to
1.050 Volts)INFO:Pack:1650 - Map created a placed design.Section 4 - Removed Logic Summary--------------------------------- 2 block(s) optimized awaySection 5 - Removed Logic-------------------------Optimized Block(s):TYPE BLOCKGND XST_GNDVCC XST_VCCTo enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+----------------------------------------------------------------------------------------------------------------------------------------+| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB || | | | | Strength | Rate | | | Delay |+----------------------------------------------------------------------------------------------------------------------------------------+| clk | IOB | INPUT | LVCMOS25 | | | | | || counter<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || counter<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || counter<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || counter<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || counter<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || counter<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || counter<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || counter<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || counter<8> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || counter<9> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || counter<10> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || counter<11> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || counter<12> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || counter<13> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || counter<14> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || counter<15> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || counter<16> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || counter<17> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || counter<18> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || counter<19> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || counter<20> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || counter<21> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || counter<22> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || counter<23> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || counter<24> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || counter<25> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || counter<26> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || counter<27> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || counter<28> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || counter<29> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || counter<30> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || counter<31> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || reset | IOB | INPUT | LVCMOS25 | | | | | |+----------------------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group and Partition Summary--------------------------------------------Partition Implementation Status------------------------------- No Partitions were found in this design.-------------------------------Area Group Information---------------------- No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------INFO:Timing:3284 - This timing report was generated using estimated delay information. For accurate numbers, please refer to the post Place and Route timing report.Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation.------------------------------------------------------------------------------------------------------ Constraint | Check | Worst Case | Best Case | Timing | Timing | | Slack | Achievable | Errors | Score ------------------------------------------------------------------------------------------------------ OFFSET = OUT 10 ns AFTER COMP "clk" | MAXDELAY| 2.448ns| 7.552ns| 0| 0------------------------------------------------------------------------------------------------------ TS_clk = PERIOD TIMEGRP "clk" 5 ns HIGH 5 | SETUP | 3.084ns| 1.916ns| 0| 0 0% | HOLD | 0.307ns| | 0| 0------------------------------------------------------------------------------------------------------ TS_upper_counter = MAXDELAY FROM TIMEGRP | SETUP | 18.093ns| 1.907ns| 0| 0 "upper_counter" TO TIMEGRP "upper_counter | HOLD | 0.520ns| | 0| 0 " TS_clk * 4 | | | | | ------------------------------------------------------------------------------------------------------All constraints were met.Section 12 - Configuration String Details-----------------------------------------Use the "-detail" map option to print out Configuration Strings⌨️ 快捷键说明
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