_primary.vhd

ISE sample code 初學者適合使用

library verilog;
use verilog.vl_types.all;
entity \sp_syn_ram-rtl\ is
    generic(
        data_width      : integer := 8;
        addr_width      : integer := 3
    );
    port(
        addr            : in     vl_logic_vector;
        data_in         : in     vl_logic_vector;
        inclk           : in     vl_logic;
        outclk          : in     vl_logic;
        we              : in     vl_logic;
        data_out        : out    vl_logic_vector
    );
end \sp_syn_ram-rtl\;