📄 mcf523x_etpu_struc.h
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/**************************************************************************/
/* FILE NAME: mcf523x_eTPU_struc.h */
/* COPYRIGHT (c) Freescale Semiconductor 2004 */
/* VERSION: 0.02 All Rights Reserved */
/* */
/* DESCRIPTION: */
/* This file contains eTPU register and bit field definitions for MCF523x.*/
/* Part of mpc5554.h auto-generated code by J.Loeliger. */
/*========================================================================*/
/* UPDATE HISTORY */
/* REV AUTHOR DATE DESCRIPTION OF CHANGE */
/* --- ----------- --------- --------------------- */
/* 0.01 J.Loeliger 30/Apr/04 Initial version of file. */
/* M.Princ */
/* 0.02 J.Loeliger 20/Jul/04 Update eTPU structure to match mpc5554.*/
/**************************************************************************/
#ifndef _MCF523x_eTPU_struc_H_
#define _MCF523x_eTPU_struc_H_
#include "typedefs.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __MWERKS__
#pragma push
#pragma ANSI_strict off
#endif
/***************************Configuration Registers**************************/
struct ETPU_tag {
union { /* MODULE CONFIGURATION REGISTER */
vuint32_t R;
struct {
vuint32_t GEC:1; /* Global Exception Clear */
vuint32_t:3;
vuint32_t MGE1:1; /* Microcode Global Exception-ETPU_A */
vuint32_t MGE2:1; /* Microcode Global Exception-ETPU_B */
vuint32_t ILF1:1; /* Illegal Instruction Flag-ETPU_A */
vuint32_t ILF2:1; /* Illegal Instruction Flag-ETPU_B */
vuint32_t:3;
vuint32_t SCMSIZE:5; /* Shared Code Memory size */
vuint32_t:5;
vuint32_t SCMMISF:1; /* SCM MISC Flag */
vuint32_t SCMMISEN:1; /* SCM MISC Enable */
vuint32_t:2;
vuint32_t VIS:1; /* SCM Visability */
vuint32_t:5;
vuint32_t GTBE:1; /* Global Time Base Enable */
} B;
} MCR;
union { /* COHERENT DUAL-PARAMETER CONTROL */
vuint32_t R;
struct {
vuint32_t STS:1; /* Start Status bit */
vuint32_t CTBASE:5; /* Channel Transfer Base */
vuint32_t PBASE:10; /* Parameter Buffer Base Address */
vuint32_t PWIDTH:1; /* Parameter Width */
vuint32_t PARAM0:7; /* Channel Parameter 0 */
vuint32_t WR:1;
vuint32_t PARAM1:7; /* Channel Parameter 1 */
} B;
} CDCR;
uint32_t etpu_reserved1;
union { /* MISC Compare Register */
uint32_t R;
} MISCCMPR;
uint32_t etpu_reserved2;
union { /* ETPU_A Configuration Register */
vuint32_t R;
struct {
vuint32_t FEND:1; /* Force END */
vuint32_t MDIS:1; /* Low power Stop */
vuint32_t:1;
vuint32_t STF:1; /* Stop Flag */
vuint32_t:4;
vuint32_t HLTF:1; /* Halt Mode Flag */
vuint32_t:4;
vuint32_t FPSCK:3; /* Filter Prescaler Clock Control */
vuint32_t CDFC:2;
vuint32_t:9;
vuint32_t ETB:5; /* Entry Table Base */
} B;
} ECR_A;
union { /* ETPU_B Configuration Register */
vuint32_t R;
struct {
vuint32_t FEND:1; /* Force END */
vuint32_t MDIS:1; /* Low power Stop */
vuint32_t:1;
vuint32_t STF:1; /* Stop Flag */
vuint32_t:4;
vuint32_t HLTF:1; /* Halt Mode Flag */
vuint32_t:4;
vuint32_t FPSCK:3; /* Filter Prescaler Clock Control */
vuint32_t CDFC:2;
vuint32_t:9;
vuint32_t ETB:5; /* Entry Table Base */
} B;
} ECR_B;
uint32_t etpu_reserved4;
union { /* ETPU_A Timebase Configuration Register */
uint32_t R;
struct {
uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */
uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */
uint32_t:1;
uint32_t AM:1; /* Angle Mode */
uint32_t:3;
uint32_t TCR2P:6; /* TCR2 Prescaler Control */
uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */
uint32_t:6;
uint32_t TCR1P:8; /* TCR1 Prescaler Control */
} B;
} TBCR_A;
union { /* ETPU_A TCR1 Visibility Register */
vuint32_t R;
} TB1R_A;
union { /* ETPU_A TCR2 Visibility Register */
vuint32_t R;
} TB2R_A;
union { /* ETPU_A STAC Configuration Register */
vuint32_t R;
struct {
vuint32_t REN1:1; /* Resource Enable TCR1 */
vuint32_t RSC1:1; /* Resource Control TCR1 */
vuint32_t VALID1:1; /* TCR1 Server Valid */
vuint32_t:9;
vuint32_t SRV1:4; /* Resource Server Slot */
vuint32_t REN2:1; /* Resource Enable TCR2 */
vuint32_t RSC2:1; /* Resource Control TCR2 */
vuint32_t VALID2:1; /* TCR2 Server Valid */
vuint32_t:9;
vuint32_t SRV2:4; /* Resource Server Slot */
} B;
} REDCR_A;
uint32_t etpu_reserved5[4];
union { /* ETPU_B Timebase Configuration Register */
uint32_t R;
struct {
uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */
uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */
uint32_t:1;
uint32_t AM:1; /* Angle Mode */
uint32_t:3;
uint32_t TCR2P:6; /* TCR2 Prescaler Control */
uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */
uint32_t:6;
uint32_t TCR1P:8; /* TCR1 Prescaler Control */
} B;
} TBCR_B;
union { /* ETPU_B TCR1 Visibility Register */
vuint32_t R;
} TB1R_B;
union { /* ETPU_B TCR2 Visibility Register */
vuint32_t R;
} TB2R_B;
union { /* ETPU_B STAC Configuration Register */
vuint32_t R;
struct {
vuint32_t REN1:1; /* Resource Enable TCR1 */
vuint32_t RSC1:1; /* Resource Control TCR1 */
vuint32_t VALID1:1; /* TCR1 Server Valid */
vuint32_t:9;
vuint32_t SRV1:4; /* Resource Server Slot */
vuint32_t REN2:1; /* Resource Enable TCR2 */
vuint32_t RSC2:1; /* Resource Control TCR2 */
vuint32_t VALID2:1; /* TCR2 Server Valid */
vuint32_t:9;
vuint32_t SRV2:4; /* Resource Server Slot */
} B;
} REDCR_B;
uint32_t etpu_reserved7[108];
/*****************************Status and Control Registers**************************/
union { /* ETPU_A Channel Interrut Status */
vuint32_t R;
struct {
vuint32_t CIS31:1; /* Channel 31 Interrut Status */
vuint32_t CIS30:1; /* Channel 30 Interrut Status */
vuint32_t CIS29:1; /* Channel 29 Interrut Status */
vuint32_t CIS28:1; /* Channel 28 Interrut Status */
vuint32_t CIS27:1; /* Channel 27 Interrut Status */
vuint32_t CIS26:1; /* Channel 26 Interrut Status */
vuint32_t CIS25:1; /* Channel 25 Interrut Status */
vuint32_t CIS24:1; /* Channel 24 Interrut Status */
vuint32_t CIS23:1; /* Channel 23 Interrut Status */
vuint32_t CIS22:1; /* Channel 22 Interrut Status */
vuint32_t CIS21:1; /* Channel 21 Interrut Status */
vuint32_t CIS20:1; /* Channel 20 Interrut Status */
vuint32_t CIS19:1; /* Channel 19 Interrut Status */
vuint32_t CIS18:1; /* Channel 18 Interrut Status */
vuint32_t CIS17:1; /* Channel 17 Interrut Status */
vuint32_t CIS16:1; /* Channel 16 Interrut Status */
vuint32_t CIS15:1; /* Channel 15 Interrut Status */
vuint32_t CIS14:1; /* Channel 14 Interrut Status */
vuint32_t CIS13:1; /* Channel 13 Interrut Status */
vuint32_t CIS12:1; /* Channel 12 Interrut Status */
vuint32_t CIS11:1; /* Channel 11 Interrut Status */
vuint32_t CIS10:1; /* Channel 10 Interrut Status */
vuint32_t CIS9:1; /* Channel 9 Interrut Status */
vuint32_t CIS8:1; /* Channel 8 Interrut Status */
vuint32_t CIS7:1; /* Channel 7 Interrut Status */
vuint32_t CIS6:1; /* Channel 6 Interrut Status */
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