cfmacreg.h

marvell wifi driver CF-8385PN-NDIS-ARM4-WINCE50-5.24.17.p5-27.p11.src.zip

/******************* (c) Marvell Semiconductor, Inc., 2004 ********************
 *
 *  Purpose:    This file contains CF MAC registers definition
 *
 *  Notes:
 *
 *
 *	$Author: schiu $
 *
 *	$Date: 2004/08/23 $
 *
 *	$Revision: #2 $
 *
 *****************************************************************************/

#ifndef __CFMACREG_H_    /* filename in CAPS */
#define __CFMACREG_H_

//
// NDIS version
//
#define MRVDRV_NDIS_MAJOR_VERSION 0x5

#ifdef MRVL_WINXP_NDIS51
#define MRVDRV_NDIS_MINOR_VERSION 0x1
#else
#define MRVDRV_NDIS_MINOR_VERSION 0x0
#endif

#define MRVDRV_DRIVER_VERSION ((MRVDRV_NDIS_MAJOR_VERSION*0x100) + MRVDRV_NDIS_MINOR_VERSION)

//
// Product name
//
#define	VENDORDESCRIPTOR "Marvell W8100 802.11 CompactFlash CARD NIC"
#define MRVL_8100_COMPACTFLASH_VER_ID           	0x02

// define CF MAC device ID
#define MRVL_8300_PCMCIA_DEVICE_ID                  	0x03

// define CF MAC I/P window size
#define CFMACREG_IO_LENGTH                          		0x50

// Host Control Registers (HCR) Offset
//
#define CFMACREG_HCR_HOST_STATUS                    		0x00000000
#define CFMACREG_HCR_CARD_INT_CAUSE                 	0x00000002
#define CFMACREG_HCR_HOST_INT_MASK                  	0x00000004
#define CFMACREG_HCR_READ_BASE_LOW                  	0x00000008
#define CFMACREG_HCR_READ_BASE_HIGH                 	0x0000000A
#define CFMACREG_HCR_WRITE_BASE_LOW                 	0x0000000C
#define CFMACREG_HCR_WRITE_BASE_HIGH                	0x0000000E
#define CFMACREG_HCR_IO_READ_PORT                   		0x00000010
#define CFMACREG_HCR_IO_CMD_READ_PORT               	0x00000012
#define CFMACREG_HCR_IO_WRITE_LEN                   		0x00000014
#define CFMACREG_HCR_IO_WRITE_PORT                  		0x00000016
#define CFMACREG_HCR_IO_CMD_WRITE_LEN               	0x00000018
#define CFMACREG_HCR_IO_CMD_WRITE_PORT             	0x0000001A

#define CFMACREG_HCR_SCRATCH_PORT                   		0x0000003F
#define CFMACREG_HCR_CIS_ADDR_PORT                  		0x00000046
#define CFMACREG_HCR_CIS_DATA_PORT                  		0x00000048
#define CFMACREG_HCR_IO_GBUS_REG_READ               	0x0000004C
#define CFMACREG_HCR_IO_GBUS_REG_WRITE              	0x0000004E

// Card Control Registers (CCR) Offset
//
#define CFMACREG_CCR_PRODUCT_ID                     		0x0000001C
#define CFMACREG_CCR_CARD_STATUS                    		0x00000020
#define CFMACREG_CCR_HOST_INT_CAUSE                 	0x00000022
#define CFMACREG_CCR_IO_READ_LEN                    		0x00000024
#define CFMACREG_CCR_SQ_READ_BASE_LOW              	0x00000028
#define CFMACREG_CCR_SQ_READ_BASE_HIGH             	0x0000002A
#define CFMACREG_CCR_SQ_WRITE_BASE_LOW             	0x0000002C
#define CFMACREG_CCR_SQ_WRITE_BASE_HIGH            	0x0000002E
#define CFMACREG_CCR_IO_CMD_READ_LEN                	0x00000030
#define CFMACREG_CCR_SQ_CMD_READ_BASE_LOW      	0x00000034
#define CFMACREG_CCR_SQ_CMD_READ_BASE_HIGH     	0x00000036
#define CFMACREG_CCR_SQ_CMD_WRITE_BASE_LOW    	0x00000038
#define CFMACREG_CCR_SQ_CMD_WRITE_BASE_HIGH   	0x0000003A
#define CFMACREG_CCR_CFG_REG_BASE_ADR               	0x0000003C
#define CFMACREG_CCR_CARD_CFG                       		0x0000003E
#define CFMACREG_CCR_SCRATCH_PORT                   		0x0000003F
#define CFMACREG_CCR_TX_FRAME_SEQ_NUM               	0x00000040
#define CFMACREG_CCR_TX_FRAME_STATUS               	0x00000042
#define CFMACREG_CCR_CARD_INT_MASK                  	0x00000044
#define CFMACREG_CCR_CIS_ADR_PORT                   		0x00000046
#define CFMACREG_CCR_CIS_DATA_PORT                  		0x00000048

// Bit definition for CFMACREG_HCR_HOST_STATUS (Host Status)
#define CFMACREG_HCR_HS_TxDnLdOvr                   	B_BIT_0
#define CFMACREG_HCR_HS_RxUpLdOvr                   	B_BIT_1
#define CFMACREG_HCR_HS_CmdDnLdOvr                  B_BIT_2
#define CFMACREG_HCR_HS_PwrDown                     	B_BIT_3
#define CFMACREG_HCR_HS_HstEvent                    	B_BIT_4
#define CFMACREG_HCR_HS_FlushDataFifo               	B_BIT_5
#define CFMACREG_HCR_HS_MASK                        	0x3F

// Bit definition for CFMACREG_HCR_CARD_INT_CAUSE (Card Interrupt Cause)
#define CFMACREG_HCR_CIC_TxDnLdOvr                  	W_BIT_0
#define CFMACREG_HCR_CIC_RxUpLdOvr                  	W_BIT_1
#define CFMACREG_HCR_CIC_CmdDnLdOvr                 W_BIT_2
#define CFMACREG_HCR_CIC_PwrDown                    	W_BIT_3
#define CFMACREG_HCR_CIC_HstEvent                  	W_BIT_4
#define CFMACREG_HCR_CIC_MASK                       	0x001F

// Bit definition for CFMACREG_HCR_HOST_INT_MASK (Host Interrupt Mask)
#define CFMACREG_HCR_HIM_TxDnLdRdy                  	W_BIT_0
#define CFMACREG_HCR_HIM_RxUpLdRdy                  	W_BIT_1
#define CFMACREG_HCR_HIM_CmdDnLdRdy                W_BIT_2
#define CFMACREG_HCR_HIM_CmdRspRdy                  W_BIT_3
#define CFMACREG_HCR_HIM_CardEvent                  	W_BIT_4
#define CFMACREG_HCR_HIM_MASK                       	0x001F


// Bit definition for CFMACREG_CCR_CARD_STATUS (Card Status)
#define CFMACREG_CCR_CS_TxDnLdRdy                   	W_BIT_0
#define CFMACREG_CCR_CS_RxUpLdRdy                   	W_BIT_1
#define CFMACREG_CCR_CS_CmdDnLdRdy                  W_BIT_2
#define CFMACREG_CCR_CS_CmdRspRdy                   	W_BIT_3
#define CFMACREG_CCR_CS_CardEvent                   	W_BIT_4
#define CFMACREG_CCR_CS_PwrDwn                      	W_BIT_8
#define CFMACREG_CCR_CS_MACErr                      	W_BIT_9
#define CFMACREG_CCR_CS_802_11LnkUp                	W_BIT_10
#define CFMACREG_CCR_CS_10btLnkUp                   	W_BIT_11
#define CFMACREG_CCR_CS_100btLnkUp                  	W_BIT_12
#define CFMACREG_CCR_CS_LnkStsChg                   	W_BIT_13
#define CFMACREG_CCR_CS_TxFrmStsChg                 	W_BIT_14
#define CFMACREG_CCR_CS_ReadCISRdy                  	W_BIT_15
#define CFMACREG_CCR_CS_MASK                        	0xFF1F
#define CFMACREG_CCR_CS_STATUS_MASK                0x7f00

// Bit definition for CFMACREG_CCR_HOST_INT_CAUSE (Host Interrupt Cause)
#define CFMACREG_CCR_HIC_TxDnLdRdy                 	W_BIT_0
#define CFMACREG_CCR_HIC_RxUpLdRdy                  	W_BIT_1
#define CFMACREG_CCR_HIC_CmdDnLdRdy                 W_BIT_2
#define CFMACREG_CCR_HIC_CmdRspRdy                  	W_BIT_3
#define CFMACREG_CCR_HIC_CardEvent                  	W_BIT_4
#define CFMACREG_CCR_HIC_MASK                       	0x001F

// Bit definition for CFMACREG_CCR_TX_FRAME_STATUS (Tx Frame Status)
#define CFMACREG_CCR_TFS_SqDmaOvr                   	W_BIT_0
#define CFMACREG_CCR_TFS_TxFrmSent                 	W_BIT_1
#define CFMACREG_CCR_TFS_RtyLmtExcd                 	W_BIT_2
#define CFMACREG_CCR_TFS_TimeOut                    	W_BIT_3
#define CFMACREG_CCR_TFS_MASK                       	0x000F

// Frame status also returns link speed in bits 4 through 7. They will be filled
//      in by FW to correspond with the link speed but in a different translation.
//      Once shifted down to low order nibble, this is the translation.      
#define FRAME_STATUS_LINK_SPEED_1mbps 			0            
#define FRAME_STATUS_LINK_SPEED_2mbps       		1               
#define FRAME_STATUS_LINK_SPEED_5dot5mbps   		2             
#define FRAME_STATUS_LINK_SPEED_11mbps      		3          
#define FRAME_STATUS_LINK_SPEED_6mbps      		5             
#define FRAME_STATUS_LINK_SPEED_9mbps      		6              
#define FRAME_STATUS_LINK_SPEED_12mbps       		7               
#define FRAME_STATUS_LINK_SPEED_18mbps       		8                
#define FRAME_STATUS_LINK_SPEED_24mbps          		9             
#define FRAME_STATUS_LINK_SPEED_36mbps      		10            
#define FRAME_STATUS_LINK_SPEED_48mbps      		11           
#define FRAME_STATUS_LINK_SPEED_54mbps      		12    

// Bit definition for CFMACREG_CCR_CARD_INT_MASK (Card Interrupt Mask)
#define CFMACREG_CCR_CIM_TxDnLdOvr                  	W_BIT_0
#define CFMACREG_CCR_CIM_RxUpLdOvr                  	W_BIT_1
#define CFMACREG_CCR_CIM_CmdDnLdOvr                 W_BIT_2
#define CFMACREG_CCR_CIM_PwrDown                    	W_BIT_3
#define CFMACREG_CCR_CIM_HstEvent                  	W_BIT_4
#define CFMACREG_CCR_CIM_MASK                       	0x001F

// Define Host to card event code used by CFMACREG_HCR_SCRATCH_PORT
#define CFMACREG_HCR_SP_RxUpLdOvr                   	B_BIT_0 // 11/25/02 - Use Scratch pad
//#define CFMACREG_HCR_SP_NONE                        	0x00
//#define CFMACREG_HCR_SP_HOST_INIT_IN_PROGRESS     0x01
//#define CFMACREG_HCR_SP_HOST_INIT_FINISHED          	0x02
//#define CFMACREG_HCR_SP_HOST_HALT_IN_PROGRESS    0x81

// Scratch register status definitions
// boot loader is ready to begin firmware download
#define CF_SCRATCH_BOOT_WAITING                     		0xc3
// Host has completed downloading a 256 byte block
#define CF_SCRATCH_HOST_BLOCK_READY                 	0x55
// boot loader as completed moving 256 byte block to memory
#define CF_SCRATCH_BOOT_BLOCK_COMPLETE              	0xaa
// Host has finished downloading firmware
#define CF_SCRATCH_HOST_DOWNLOAD_COMPLETE       	0x00
// Firmware is up and running
#define CF_SCRATCH_FIRMWARE_READY                   		0x5a

// INT code register event definition
#define MACREG_INT_CODE_TX_PPA_FREE         			0x00000000 
#define MACREG_INT_CODE_TX_DMA_DONE         		0x00000001
#define MACREG_INT_CODE_LINK_LOSE_W_SCAN    		0x00000002
#define MACREG_INT_CODE_LINK_LOSE_NO_SCAN   		0x00000003
#define MACREG_INT_CODE_LINK_SENSED         			0x00000004
#define MACREG_INT_CODE_CMD_FINISHED        		0x00000005
#define MACREG_INT_CODE_MIB_CHANGED         		0x00000006 
#define MACREG_INT_CODE_INIT_DONE           			0x00000007 
#define MACREG_INT_CODE_DEAUTHENTICATED     		0x00000008 
#define MACREG_INT_CODE_DISASSOCIATED       		0x00000009 
#define MACREG_INT_CODE_PS_AWAKE					0x0000000a 
#define MACREG_INT_CODE_PS_SLEEP					0x0000000b 
#define MACREG_INT_CODE_WPA_MIC_ERR_MULTICAST  0x0000000d
#define MACREG_INT_CODE_WPA_MIC_ERR_UNICAST 	0x0000000e       
#define MACREG_INT_CODE_HOST_AWAKE              		0x0000000f
#define MACREG_INT_CODE_DS_AWAKE                		0x00000010 
#define MACREG_INT_CODE_ADHOC_BCN_LOST          	0x00000011

#ifdef HOST_WAKEUP  
#define MACREG_INT_CODE_HOST_WAKE_UP                0x00000012
#endif

#ifdef BG_SCAN
#define MACREG_INT_CODE_BG_SCAN_REPORT			0x00000018 
#endif

#define MACREG_INT_CODE_RSSI_LOW                    0x00000019
#define MACREG_INT_CODE_SNR_LOW                     0x0000001a
#define MACREG_INT_CODE_MAX_FAIL                    0x0000001b

/*
===============================================================================
                            PUBLIC TYPE DEFINITIONS
===============================================================================
*/

#else
#endif /* _FILENAME_H_ */