dmasm.vhd

here is a VHDL example

library ieee;
use ieee.std_logic_1164.all;
entity DMASM is
port (A,B,C,D: in bit;
PBGNT, MACK, CONT : in bit;
RST, CLK : in bit;
PBREQ, CMREQ, CE, CNTLD, CLD : out bit);
end DMASM;
architecture BEHAVE of DMASM is
type STATE is (S0, S1, S2, S3, S4, S5);
signal CURRENT_STATE, NEXT_STATE: STATE;
begin
SEQ: process (RST, CLK)
begin
if (RST = '0') then
CURRENT_STATE <= S0;
elsif (CLK' event and CLK = '1' ) then
CURRENT_STATE <= NEXT_STATE;
end if;
end process;
COMB: process (CURRENT_STATE, A, B, C, D, PBGNT, MACK, CONT)
begin
PBREQ <= '0';
CMREQ <= '0';
CE <= '0';
CNTLD <= '0';
CLD <= '0';
case CURRENT_STATE is
when S0 =>
if (A = '1' or B = '1' or C = '1' or D = '1') then
NEXT_STATE <= S1;
else
NEXT_STATE <= S0;
end if;
when S1 => PBREQ <= '1';
if (PBGNT = '1') then
NEXT_STATE <= S2;
else
NEXT_STATE <= S1;
end if;
when S2 => CNTLD <= '1'; CMREQ <= '1';
if (MACK = '1') then
NEXT_STATE <= S3;
else
NEXT_STATE <= S2;
end if;
when S3 => CE <= '1';
NEXT_STATE <= S4;
when S4 => CLD <= '1';
if (CONT = '1') then
NEXT_STATE <= S5;
else
NEXT_STATE <= S0;
end if;
when S5 => CMREQ <= '1';
if (MACK = '1') then
NEXT_STATE <= S3;
else
NEXT_STATE <= S5;
end if;
end case;
end process;
end BEHAVE;