m.vhd

M序列的源代码

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
entity m is
port(clock: in STD_LOGIC;
dat: out STD_LOGIC);
end m;

architecture m_arch of m is
signal m:std_logic_vector(4 downto 0);
begin
m_sequence_form:process(clock)
begin
 if(clock'event and clock='1') then
      m(1)<= m(0);
      m(2)<= m(1);
      m(3)<= m(2);
      m(4)<= m(3);
  end if;
end process;

process(clock)
begin
   if(clock'event and clock='1') then
      m(0)<=not(m(4)xor m(1));
   end if;
end process;
dat<=m(0);
end m_arch;