sfr62p.inc

瑞萨(Renesas)M16C系列芯片上实现接受摇控板控制的程序

;	Timer A0 mode register
;-----------------------------------------------------------
ta0mr			.equ		0396h
;
tmod0_ta0mr		.btequ		0,ta0mr		; Operation mode select bit
tmod1_ta0mr		.btequ		1,ta0mr		; Operation mode select bit
mr0_ta0mr		.btequ		2,ta0mr		;
mr1_ta0mr		.btequ		3,ta0mr		;
mr2_ta0mr		.btequ		4,ta0mr		;
mr3_ta0mr		.btequ		5,ta0mr		;
tck0_ta0mr		.btequ		6,ta0mr		; Count source select bit
tck1_ta0mr		.btequ		7,ta0mr		; Count source select bit
;
;-----------------------------------------------------------
;	Timer A1 mode register
;-----------------------------------------------------------
ta1mr			.equ		0397h
;
tmod0_ta1mr		.btequ		0,ta1mr		; Operation mode select bit
tmod1_ta1mr		.btequ		1,ta1mr		; Operation mode select bit
mr0_ta1mr		.btequ		2,ta1mr		;
mr1_ta1mr		.btequ		3,ta1mr		;
mr2_ta1mr		.btequ		4,ta1mr		;
mr3_ta1mr		.btequ		5,ta1mr		;
tck0_ta1mr		.btequ		6,ta1mr		; Count source select bit
tck1_ta1mr		.btequ		7,ta1mr		; Count source select bit
;
;-----------------------------------------------------------
;	Timer A2 mode register
;-----------------------------------------------------------
ta2mr			.equ		0398h
;
tmod0_ta2mr		.btequ		0,ta2mr		; Operation mode select bit
tmod1_ta2mr		.btequ		1,ta2mr		; Operation mode select bit
mr0_ta2mr		.btequ		2,ta2mr		;
mr1_ta2mr		.btequ		3,ta2mr		;
mr2_ta2mr		.btequ		4,ta2mr		;
mr3_ta2mr		.btequ		5,ta2mr		;
tck0_ta2mr		.btequ		6,ta2mr		; Count source select bit
tck1_ta2mr		.btequ		7,ta2mr		; Count source select bit
;
;-----------------------------------------------------------
;	Timer A3 mode register
;-----------------------------------------------------------
ta3mr			.equ		0399h
;
tmod0_ta3mr		.btequ		0,ta3mr		; Operation mode select bit
tmod1_ta3mr		.btequ		1,ta3mr		; Operation mode select bit
mr0_ta3mr		.btequ		2,ta3mr		;
mr1_ta3mr		.btequ		3,ta3mr		;
mr2_ta3mr		.btequ		4,ta3mr		;
mr3_ta3mr		.btequ		5,ta3mr		;
tck0_ta3mr		.btequ		6,ta3mr		; Count source select bit
tck1_ta3mr		.btequ		7,ta3mr		; Count source select bit
;
;-----------------------------------------------------------
;	Timer A4 mode register
;-----------------------------------------------------------
ta4mr			.equ		039ah
;
tmod0_ta4mr		.btequ		0,ta4mr		; Operation mode select bit
tmod1_ta4mr		.btequ		1,ta4mr		; Operation mode select bit
mr0_ta4mr		.btequ		2,ta4mr		;
mr1_ta4mr		.btequ		3,ta4mr		;
mr2_ta4mr		.btequ		4,ta4mr		;
mr3_ta4mr		.btequ		5,ta4mr		;
tck0_ta4mr		.btequ		6,ta4mr		; Count source select bit
tck1_ta4mr		.btequ		7,ta4mr		; Count source select bit
;
;-----------------------------------------------------------
;	Timer B0 mode register
;-----------------------------------------------------------
tb0mr			.equ		039bh
;
tmod0_tb0mr		.btequ		0,tb0mr		; Operation mode select bit
tmod1_tb0mr		.btequ		1,tb0mr		; Operation mode select bit
mr0_tb0mr		.btequ		2,tb0mr		;
mr1_tb0mr		.btequ		3,tb0mr		;
mr2_tb0mr		.btequ		4,tb0mr		;
mr3_tb0mr		.btequ		5,tb0mr		;
tck0_tb0mr		.btequ		6,tb0mr		; Count source select bit
tck1_tb0mr		.btequ		7,tb0mr		; Count source select bit
;
;-----------------------------------------------------------
;	Timer B1 mode register
;-----------------------------------------------------------
tb1mr			.equ		039ch
;
tmod0_tb1mr		.btequ		0,tb1mr		; Operation mode select bit
tmod1_tb1mr		.btequ		1,tb1mr		; Operation mode select bit
mr0_tb1mr		.btequ		2,tb1mr		;
mr1_tb1mr		.btequ		3,tb1mr		;
mr3_tb1mr		.btequ		5,tb1mr		;
tck0_tb1mr		.btequ		6,tb1mr		; Count source select bit
tck1_tb1mr		.btequ		7,tb1mr		; Count source select bit
;
;-----------------------------------------------------------
;	Timer B2 mode register
;-----------------------------------------------------------
tb2mr			.equ		039dh
;
tmod0_tb2mr		.btequ		0,tb2mr		; Operation mode select bit
tmod1_tb2mr		.btequ		1,tb2mr		; Operation mode select bit
mr0_tb2mr		.btequ		2,tb2mr		;
mr1_tb2mr		.btequ		3,tb2mr		;
mr3_tb2mr		.btequ		5,tb2mr		;
tck0_tb2mr		.btequ		6,tb2mr		; Count source select bit
tck1_tb2mr		.btequ		7,tb2mr		; Count source select bit
;
;-----------------------------------------------------------
;	Timer B2 special mode register
;-----------------------------------------------------------
tb2sc			.equ		039eh
;
pwcon			.btequ		0,tb2sc		; Timer B2 reload taiming switching bit
ivpcr1			.btequ		1,tb2sc		; Three phase output port NMI control bit 1
;
;-------------------------------------------------------
;	UART0 transmit/receive mode register
;-------------------------------------------------------
u0mr			.equ		03a0h
;
smd0_u0mr		.btequ		0,u0mr		; Serial I/O mode select bit
smd1_u0mr		.btequ		1,u0mr		; Serial I/O mode select bit
smd2_u0mr		.btequ		2,u0mr		; Serial I/O mode select bit
ckdir_u0mr		.btequ		3,u0mr		; Internal/external clock select bit
stps_u0mr		.btequ		4,u0mr		; Stop bit length select bit
pry_u0mr		.btequ		5,u0mr		; Odd/even parity select bit
prye_u0mr		.btequ		6,u0mr		; Parity enable bit
iopol_u0mr		.btequ		7,u0mr		; TxD,RxD I/O polarity reverse bit
;
;-------------------------------------------------------
;	UART0 bit rate generator ; Use "MOV" instruction when writing to this register.
;-------------------------------------------------------
u0brg			.equ		03a1h
;
;-------------------------------------------------------
;	UART0 transmit buffer register ; Use "MOV" instruction when writing to this register.
;-------------------------------------------------------
u0tb			.equ		03a2h
u0tbl			.equ		u0tb		;		Low
u0tbh			.equ		u0tb+1		;		High
;
;-------------------------------------------------------
;	UART0 transmit/receive control register 0
;-------------------------------------------------------
u0c0			.equ		03a4h
;
clk0_u0c0		.btequ		0,u0c0		; BRG count source select bit
clk1_u0c0		.btequ		1,u0c0		; BRG count source select bit
crs_u0c0		.btequ		2,u0c0		; CTS~/RTS~ function select bit
txept_u0c0		.btequ		3,u0c0		; Transmit register empty flag
crd_u0c0		.btequ		4,u0c0		; CTS~/RTS~ disable bit
nch_u0c0		.btequ		5,u0c0		; Data output select bit
ckpol_u0c0		.btequ		6,u0c0		; CLK polarity select bit
uform_u0c0		.btequ		7,u0c0		; Transfer format select bit
;
;-------------------------------------------------------
;	UART0 transmit/receive control register 1
;-------------------------------------------------------
u0c1			.equ		03a5h
;
te_u0c1			.btequ		0,u0c1		; Transmit enable bit
ti_u0c1			.btequ		1,u0c1		; Transmit buffer empty flag
re_u0c1			.btequ		2,u0c1		; Receive enable bit
ri_u0c1			.btequ		3,u0c1		; Receive complete flag
u0lch			.btequ		6,u0c1		; Data logic select bit
u0ere			.btequ		7,u0c1		; Error signal output enable bit
;
;-------------------------------------------------------
;	UART0 receive buffer register
;-------------------------------------------------------
u0rb			.equ		03a6h
u0rbl			.equ		u0rb		;		Low
u0rbh			.equ		u0rb+1		;		High
abt_u0rb		.btequ		3,u0rbh		; Arbitrastion lost detecting flag
oer_u0rb		.btequ		4,u0rbh		; Overrun error flag
fer_u0rb		.btequ		5,u0rbh		; Framing error flag
per_u0rb		.btequ		6,u0rbh		; Parity error flag
sum_u0rb		.btequ		7,u0rbh		; Error sum flag
;
;-------------------------------------------------------
;	UART1 transmit/receive mode register
;-------------------------------------------------------
u1mr			.equ		03a8h
;
smd0_u1mr		.btequ		0,u1mr		; Serial I/O mode select bit
smd1_u1mr		.btequ		1,u1mr		; Serial I/O mode select bit
smd2_u1mr		.btequ		2,u1mr		; Serial I/O mode select bit
ckdir_u1mr		.btequ		3,u1mr		; Internal/external clock select bit
stps_u1mr		.btequ		4,u1mr		; Stop bit length select bit
pry_u1mr		.btequ		5,u1mr		; Odd/even parity select bit
prye_u1mr		.btequ		6,u1mr		; Parity enable bit
iopol_u1mr		.btequ		7,u1mr		; TxD,RxD I/O polarity reverse bit
;
;-------------------------------------------------------
;	UART1 bit rate generator ; Use "MOV" instruction when writing to this register.
;-------------------------------------------------------
u1brg			.equ		03a9h
;
;-------------------------------------------------------
;	UART1 transmit buffer register ; Use "MOV" instruction when writing to this register.
;-------------------------------------------------------
u1tb			.equ		03aah
u1tbl			.equ		u1tb		;		Low
u1tbh			.equ		u1tb+1		;		High
;
;-------------------------------------------------------
;	UART1 transmit/receive control register 0
;-------------------------------------------------------
u1c0			.equ		03ach
;
clk0_u1c0		.btequ		0,u1c0		; BRG count source select bit
clk1_u1c0		.btequ		1,u1c0		; BRG count source select bit
crs_u1c0		.btequ		2,u1c0		; CTS~/RTS~ function select bit
txept_u1c0		.btequ		3,u1c0		; Transmit register empty flag
crd_u1c0		.btequ		4,u1c0		; CTS~/RTS~ disable bit
nch_u1c0		.btequ		5,u1c0		; Data output select bit
ckpol_u1c0		.btequ		6,u1c0		; CLK polarity select bit
uform_u1c0		.btequ		7,u1c0		; Transfer format select bit
;
;-------------------------------------------------------
;	UART1 transmit/receive control register 1
;-------------------------------------------------------
u1c1			.equ		03adh
;
te_u1c1			.btequ		0,u1c1		; Transmit enable bit
ti_u1c1			.btequ		1,u1c1		; Transmit buffer empty flag
re_u1c1			.btequ		2,u1c1		; Receive enable bit
ri_u1c1			.btequ		3,u1c1		; Receive complete flag
u1lch			.btequ		6,u1c1		; Data logic select bit
u1ere			.btequ		7,u1c1		; Error signal output enable bit
;
;-------------------------------------------------------
;	UART1 receive buffer register
;-------------------------------------------------------
u1rb			.equ		03aeh
u1rbl			.equ		u1rb		;		Low
u1rbh			.equ		u1rb+1		;		High
abt_u1rb		.btequ		3,u1rbh		; Arbitrastion lost detecting flag
oer_u1rb		.btequ		4,u1rbh		; Overrun error flag
fer_u1rb		.btequ		5,u1rbh		; Framing error flag
per_u1rb		.btequ		6,u1rbh		; Parity error flag
sum_u1rb		.btequ		7,u1rbh		; Error sum flag
;
;-------------------------------------------------------
;	UART transmit/receive control register 2
;-------------------------------------------------------
ucon			.equ		03b0h
;
u0irs			.btequ		0,ucon		; UART0 transmit interrupt cause select bit
u1irs			.btequ		1,ucon		; UART1 transmit interrupt cause select bit
u0rrm			.btequ		2,ucon		; UART0 continuous receive mode enable bit
u1rrm			.btequ		3,ucon		; UART1 continuous receive mode enable bit
clkmd0			.btequ		4,ucon		; CLK/CLKS select bit 0
clkmd1			.btequ		5,ucon		; CLK/CLKS select bit 1
rcsp			.btequ		6,ucon		; Separate CTS~/RTS~ bit
;
;--------------------------------------------------------
;	DMA0 request cause select register
;--------------------------------------------------------
dm0sl			.equ		03b8h
;
dsel0_dm0sl		.btequ		0,dm0sl		; DMA request cause select bit
dsel1_dm0sl		.btequ		1,dm0sl		; DMA request cause select bit
dsel2_dm0sl		.btequ		2,dm0sl		; DMA request cause select bit
dsel3_dm0sl		.btequ		3,dm0sl		; DMA request cause select bit
dms_dm0sl		.btequ		6,dm0sl		; DMA request cause expansion select bit
dsr_dm0sl		.btequ		7,dm0sl		; Software DMA request bit
;
;--------------------------------------------------------
;	DMA1 request cause select register
;--------------------------------------------------------
dm1sl			.equ		03bah
;
dsel0_dm1sl		.btequ		0,dm1sl		; DMA request cause select bit
dsel1_dm1sl		.btequ		1,dm1sl		; DMA request cause select bit
dsel2_dm1sl		.btequ		2,dm1sl		; DMA request cause select bit
dsel3_dm1sl		.btequ		3,dm1sl		; DMA request cause select bit
dms_dm1sl		.btequ		6,dm1sl		; DMA request cause expansion select bit
dsr_dm1sl		.btequ		7,dm1sl		; Software DMA request bit
;
;-------------------------------------------------------
;	CRC data register
;-------------------------------------------------------
crcd			.equ		03bch
crcdl			.equ		crcd		;		Low
crcdh			.equ		crcd+1		;		High
;
;-------------------------------------------------------
;	CRC input register
;-------------------------------------------------------
crcin			.equ		03beh
;
;-------------------------------------------------------
;	A/D register 0
;-------------------------------------------------------
ad0				.equ		03c0h
ad0l			.equ		ad0			;		Low
ad0h			.equ		ad0+1		;		High
;
;-------------------------------------------------------
;	A/D register 1
;-------------------------------------------------------
ad1