📄 sfr62p.inc
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stpreq_u0smr4 .btequ 2,u0smr4 ; Stop condition generate bit
stspsel_u0smr4 .btequ 3,u0smr4 ; SCL,SDA output select bit
ackd_u0smr4 .btequ 4,u0smr4 ; ACK data bit
ackc_u0smr4 .btequ 5,u0smr4 ; ACK data output enable bit
sclhi_u0smr4 .btequ 6,u0smr4 ; SCL output stop enable bit
swc9_u0smr4 .btequ 7,u0smr4 ; Final bit L hold enable bit
;
;-------------------------------------------------------
; UART0 special mode register 3
;-------------------------------------------------------
u0smr3 .equ 036dh
;
ckph_u0smr3 .btequ 1,u0smr3 ; Clock phase set bit
nodc_u0smr3 .btequ 3,u0smr3 ; Clock output select bit
dl0_u0smr3 .btequ 5,u0smr3 ; SDA0(TxD0) digital delay setup bit
dl1_u0smr3 .btequ 6,u0smr3 ; SDA0(TxD0) digital delay setup bit
dl2_u0smr3 .btequ 7,u0smr3 ; SDA0(TxD0) digital delay setup bit
;
;-------------------------------------------------------
; UART0 special mode register 2
;-------------------------------------------------------
u0smr2 .equ 036eh
;
iicm2_u0smr2 .btequ 0,u0smr2 ; IIC mode selection bit 2
csc_u0smr2 .btequ 1,u0smr2 ; Clock-synchronous bit
swc_u0smr2 .btequ 2,u0smr2 ; SCL wait output bit
als_u0smr2 .btequ 3,u0smr2 ; SDA output stop bit
stac_u0smr2 .btequ 4,u0smr2 ; UART0 initialization bit
swc2_u0smr2 .btequ 5,u0smr2 ; SCL wait output bit 2
sdhi_u0smr2 .btequ 6,u0smr2 ; SDA output disable bit
;
;-------------------------------------------------------
; UART0 special mode register
;-------------------------------------------------------
u0smr .equ 036fh
;
iicm_u0smr .btequ 0,u0smr ; IIC mode selection bit
abc_u0smr .btequ 1,u0smr ; Arbitration lost detecting flag control bit
bbs_u0smr .btequ 2,u0smr ; Bus busy flag
lsyn_u0smr .btequ 3,u0smr ; SCLL sync output enable bit
abscs_u0smr .btequ 4,u0smr ; Bus collision detect sampring clock select bit
acse_u0smr .btequ 5,u0smr ; Auto clear function select bit of transmit enable bit
sss_u0smr .btequ 6,u0smr ; Transmit start condition select bit
;
;-------------------------------------------------------
; UART1 special mode register 4
;-------------------------------------------------------
u1smr4 .equ 0370h
;
stareq_u1smr4 .btequ 0,u1smr4 ; Start condition generate bit
rstareq_u1smr4 .btequ 1,u1smr4 ; Restart condition generate bit
stpreq_u1smr4 .btequ 2,u1smr4 ; Stop condition generate bit
stspsel_u1smr4 .btequ 3,u1smr4 ; SCL,SDA output select bit
ackd_u1smr4 .btequ 4,u1smr4 ; ACK data bit
ackc_u1smr4 .btequ 5,u1smr4 ; ACK data output enable bit
sclhi_u1smr4 .btequ 6,u1smr4 ; SCL output stop enable bit
swc9_u1smr4 .btequ 7,u1smr4 ; Final bit L hold enable bit
;
;-------------------------------------------------------
; UART1 special mode register 3
;-------------------------------------------------------
u1smr3 .equ 0371h
;
ckph_u1smr3 .btequ 1,u1smr3 ; Clock phase set bit
nodc_u1smr3 .btequ 3,u1smr3 ; Clock output select bit
dl0_u1smr3 .btequ 5,u1smr3 ; SDA1(TxD1) digital delay setup bit
dl1_u1smr3 .btequ 6,u1smr3 ; SDA1(TxD1) digital delay setup bit
dl2_u1smr3 .btequ 7,u1smr3 ; SDA1(TxD1) digital delay setup bit
;
;-------------------------------------------------------
; UART1 special mode register 2
;-------------------------------------------------------
u1smr2 .equ 0372h
;
iicm2_u1smr2 .btequ 0,u1smr2 ; IIC mode selection bit 2
csc_u1smr2 .btequ 1,u1smr2 ; Clock-synchronous bit
swc_u1smr2 .btequ 2,u1smr2 ; SCL wait output bit
als_u1smr2 .btequ 3,u1smr2 ; SDA output stop bit
stac_u1smr2 .btequ 4,u1smr2 ; UART0 initialization bit
swc2_u1smr2 .btequ 5,u1smr2 ; SCL wait output bit 2
sdhi_u1smr2 .btequ 6,u1smr2 ; SDA output disable bit
;
;-------------------------------------------------------
; UART1 special mode register
;-------------------------------------------------------
u1smr .equ 0373h
;
iicm_u1smr .btequ 0,u1smr ; IIC mode selection bit
abc_u1smr .btequ 1,u1smr ; Arbitration lost detecting flag control bit
bbs_u1smr .btequ 2,u1smr ; Bus busy flag
lsyn_u1smr .btequ 3,u1smr ; SCLL sync output enable bit
abscs_u1smr .btequ 4,u1smr ; Bus collision detect sampring clock select bit
acse_u1smr .btequ 5,u1smr ; Auto clear function select bit of transmit enable bit
sss_u1smr .btequ 6,u1smr ; Transmit start condition select bit
;
;-------------------------------------------------------
; UART2 special mode register 4
;-------------------------------------------------------
u2smr4 .equ 0374h
;
stareq_u2smr4 .btequ 0,u2smr4 ; Start condition generate bit
rstareq_u2smr4 .btequ 1,u2smr4 ; Restart condition generate bit
stpreq_u2smr4 .btequ 2,u2smr4 ; Stop condition generate bit
stspsel_u2smr4 .btequ 3,u2smr4 ; SCL,SDA output select bit
ackd_u2smr4 .btequ 4,u2smr4 ; ACK data bit
ackc_u2smr4 .btequ 5,u2smr4 ; ACK data output enable bit
sclhi_u2smr4 .btequ 6,u2smr4 ; SCL output stop enable bit
swc9_u2smr4 .btequ 7,u2smr4 ; Final bit L hold enable bit
;
;-------------------------------------------------------
; UART2 special mode register 3
;-------------------------------------------------------
u2smr3 .equ 0375h
;
ckph_u2smr3 .btequ 1,u2smr3 ; Clock phase set bit
nodc_u2smr3 .btequ 3,u2smr3 ; Clock output select bit
dl0_u2smr3 .btequ 5,u2smr3 ; SDA2(TxD2) digital delay setup bit
dl1_u2smr3 .btequ 6,u2smr3 ; SDA2(TxD2) digital delay setup bit
dl2_u2smr3 .btequ 7,u2smr3 ; SDA2(TxD2) digital delay setup bit
;
;-------------------------------------------------------
; UART2 special mode register 2
;-------------------------------------------------------
u2smr2 .equ 0376h
;
iicm2_u2smr2 .btequ 0,u2smr2 ; IIC mode selection bit 2
csc_u2smr2 .btequ 1,u2smr2 ; Clock-synchronous bit
swc_u2smr2 .btequ 2,u2smr2 ; SCL wait output bit
als_u2smr2 .btequ 3,u2smr2 ; SDA output stop bit
stac_u2smr2 .btequ 4,u2smr2 ; UART0 initialization bit
swc2_u2smr2 .btequ 5,u2smr2 ; SCL wait output bit 2
sdhi_u2smr2 .btequ 6,u2smr2 ; SDA output disable bit
;
;-------------------------------------------------------
; UART2 special mode register
;-------------------------------------------------------
u2smr .equ 0377h
;
iicm_u2smr .btequ 0,u2smr ; IIC mode selection bit
abc_u2smr .btequ 1,u2smr ; Arbitration lost detecting flag control bit
bbs_u2smr .btequ 2,u2smr ; Bus busy flag
lsyn_u2smr .btequ 3,u2smr ; SCLL sync output enable bit
abscs_u2smr .btequ 4,u2smr ; Bus collision detect sampring clock select bit
acse_u2smr .btequ 5,u2smr ; Auto clear function select bit of transmit enable bit
sss_u2smr .btequ 6,u2smr ; Transmit start condition select bit
;
;-------------------------------------------------------
; UART2 transmit/receive mode register
;-------------------------------------------------------
u2mr .equ 0378h
;
smd0_u2mr .btequ 0,u2mr ; Serial I/O mode select bit
smd1_u2mr .btequ 1,u2mr ; Serial I/O mode select bit
smd2_u2mr .btequ 2,u2mr ; Serial I/O mode select bit
ckdir_u2mr .btequ 3,u2mr ; Internal/external clock select bit
stps_u2mr .btequ 4,u2mr ; Stop bit length select bit
pry_u2mr .btequ 5,u2mr ; Odd/even parity select bit
prye_u2mr .btequ 6,u2mr ; Parity enable bit
iopol_u2mr .btequ 7,u2mr ; TxD,RxD I/O polarity reverse bit
;
;-------------------------------------------------------
; UART2 bit rate generator ; Use "MOV" instruction when writing to this register.
;-------------------------------------------------------
u2brg .equ 0379h
;
;-------------------------------------------------------
; UART2 transmit buffer register ; Use "MOV" instruction when writing to this register.
;-------------------------------------------------------
u2tb .equ 037ah
u2tbl .equ u2tb ; Low
u2tbh .equ u2tb+1 ; High
;
;-------------------------------------------------------
; UART2 transmit/receive control register 0
;-------------------------------------------------------
u2c0 .equ 037ch
;
clk0_u2c0 .btequ 0,u2c0 ; BRG count source select bit
clk1_u2c0 .btequ 1,u2c0 ; BRG count source select bit
crs_u2c0 .btequ 2,u2c0 ; CTS~/RTS~ function select bit
txept_u2c0 .btequ 3,u2c0 ; Transmit register empty flag
crd_u2c0 .btequ 4,u2c0 ; CTS~/RTS~ disable bit
nch_u2c0 .btequ 5,u2c0 ; Data output select bit
ckpol_u2c0 .btequ 6,u2c0 ; CLK polarity select bit
uform_u2c0 .btequ 7,u2c0 ; Transfer format select bit
;
;-------------------------------------------------------
; UART2 transmit/receive control register 1
;-------------------------------------------------------
u2c1 .equ 037dh
;
te_u2c1 .btequ 0,u2c1 ; Transmit enable bit
ti_u2c1 .btequ 1,u2c1 ; Transmit buffer empty flag
re_u2c1 .btequ 2,u2c1 ; Receive enable bit
ri_u2c1 .btequ 3,u2c1 ; Receive complete flag
u2irs .btequ 4,u2c1 ; UART2 transmit interrupt cause select bit
u2rrm .btequ 5,u2c1 ; UART2 continuous receive mode enable bit
u2lch .btequ 6,u2c1 ; Data logic select bit
u2ere .btequ 7,u2c1 ; Error signal output enable bit
;
;-------------------------------------------------------
; UART2 receive buffer register
;-------------------------------------------------------
u2rb .equ 037eh
u2rbl .equ u2rb ; Low
u2rbh .equ u2rb+1 ; High
abt_u2rb .btequ 3,u2rbh ; Arbitrastion lost detecting flag
oer_u2rb .btequ 4,u2rbh ; Overrun error flag
fer_u2rb .btequ 5,u2rbh ; Framing error flag
per_u2rb .btequ 6,u2rbh ; Parity error flag
sum_u2rb .btequ 7,u2rbh ; Error sum flag
;
;-------------------------------------------------------
; Count start flag
;-------------------------------------------------------
tabsr .equ 0380h
;
ta0s .btequ 0,tabsr ; Timer A0 count start flag
ta1s .btequ 1,tabsr ; Timer A1 count start flag
ta2s .btequ 2,tabsr ; Timer A2 count start flag
ta3s .btequ 3,tabsr ; Timer A3 count start flag
ta4s .btequ 4,tabsr ; Timer A4 count start flag
tb0s .btequ 5,tabsr ; Timer B0 count start flag
tb1s .btequ 6,tabsr ; Timer B1 count start flag
tb2s .btequ 7,tabsr ; Timer B2 count start flag
;
;-------------------------------------------------------
; Clock prescaler reset flag
;-------------------------------------------------------
cpsrf .equ 0381h
;
cpsr .btequ 7,cpsrf ; Clock prescaler reset flag
;
;-------------------------------------------------------
; One-shot start flag
;-------------------------------------------------------
onsf .equ 0382h
;
ta0os .btequ 0,onsf ; Timer A0 one-shot start flag
ta1os .btequ 1,onsf ; Timer A1 one-shot start flag
ta2os .btequ 2,onsf ; Timer A2 one-shot start flag
ta3os .btequ 3,onsf ; Timer A3 one-shot start flag
ta4os .btequ 4,onsf ; Timer A4 one-shot start flag
tazie .btequ 5,onsf ; Z-phase input enable bit
ta0tgl .btequ 6,onsf ; Timer A0 event/trigger select bit
ta0tgh .btequ 7,onsf ; Timer A0 event/trigger select bit
;
;-------------------------------------------------------
; Trigger select register
;-------------------------------------------------------
trgsr .equ 0383h
;
ta1tgl .btequ 0,trgsr ; Timer A1 event/trigger select bit
ta1tgh .btequ 1,trgsr ; Timer A1 event/trigger select bit
ta2tgl .btequ 2,trgsr ; Timer A2 event/trigger select bit
ta2tgh .btequ 3,trgsr ; Timer A2 event/trigger select bit
ta3tgl .btequ 4,trgsr ; Timer A3 event/trigger select bit
ta3tgh .btequ 5,trgsr ; Timer A3 event/trigger select bit
ta4tgl .btequ 6,trgsr ; Timer A4 event/trigger select bit
ta4tgh .btequ 7,trgsr ; Timer A4 event/trigger select bit
;
;-------------------------------------------------------
; Up/down flag ; Use "MOV" instruction when writing to this register.
;-------------------------------------------------------
udf .equ 0384h
;
;-----------------------------------------------------------
; Timer A0 register : Read and write data in 16-bit unit.
;-----------------------------------------------------------
ta0 .equ 0386h
;
;-----------------------------------------------------------
; Timer A1 register : Read and write data in 16-bit unit.
;-----------------------------------------------------------
ta1 .equ 0388h
;
;-----------------------------------------------------------
; Timer A2 register : Read and write data in 16-bit unit.
;-----------------------------------------------------------
ta2 .equ 038ah
;
;-----------------------------------------------------------
; Timer A3 register : Read and write data in 16-bit unit.
;-----------------------------------------------------------
ta3 .equ 038ch
;
;-----------------------------------------------------------
; Timer A4 register : Read and write data in 16-bit unit.
;-----------------------------------------------------------
ta4 .equ 038eh
;
;-----------------------------------------------------------
; Timer B0 register : Read and write data in 16-bit unit.
;-----------------------------------------------------------
tb0 .equ 0390h
;
;-----------------------------------------------------------
; Timer B1 register : Read and write data in 16-bit unit.
;-----------------------------------------------------------
tb1 .equ 0392h
;
;-----------------------------------------------------------
; Timer B2 register : Read and write data in 16-bit unit.
;-----------------------------------------------------------
tb2 .equ 0394h
;
;-----------------------------------------------------------
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