sfr62p.inc

瑞萨(Renesas)M16C系列芯片上实现接受摇控板控制的程序

;------------------------------------------------------------------------
;                                                                       |
;   FILE        :sfr62p.inc                                             |
;   DATE        :Sun, Jul 27, 2008                                      |
;   DESCRIPTION :define the sfr register. (for Assembler language)      |
;   CPU GROUP   :62P                                                    |
;                                                                       |
;   This file is generated by Renesas Project Generator (Ver.4.8).      |
;                                                                       |
;------------------------------------------------------------------------

;************************************************************************************
;*																					*
;*	file name	: definition of M16C/62P's SFR										*
;*																					*
;*	Copyright, 2003 RENESAS TECHNOLOGY CORPORATION									*
;*					AND RENESAS SOLUTIONS CORPORATION								*
;*																					*
;*	Version		: 1.00 ( 2002- 7-22 ) Initial										*
;*				: 2.00 ( 2002-12-27 ) 												*
;*				: 		cm3		 register delete									*
;*				: 		vcr1	 register add										*
;*				: 		vcr2	 register add										*
;*				: 		d4int	 register add										*
;*				: 		u1bcnic	 register add										*
;*				: 		u0bcnic	 register add										*
;*				: 		wdc5	 bit add	(wdc register) 							*
;*				: 		plc06	 bit add	(plc0 register) 						*
;*				: 		pm21	 bit add	(pm2 register) 							*
;*				: 		pm22	 bit add	(pm2 register) 							*
;*				: 		fidr 	 register 											*
;*				: 				 3B4h => 1B4h										*
;*				:		fmr03	 bit delete	(fmr0 register)							*
;*				:		fmstp	 bit add	(fmr0 register)							*
;*				: 2.02 ( 2004-04-16 ) 												*
;*				: 		prc3	 bit add	(prcr register) 						*
;************************************************************************************
;
;  note:
;	This data is a freeware that SFR for M16C/62P groups is described.
;	Renesas Technology Corporation and Renesas Solutions Corporation
;	assumes no responsibility for any damage that occurred by this data.
;
;-------------------------------------------------------
;	Processor mode register 0
;-------------------------------------------------------
pm0				.equ		0004h
;
pm00			.btequ		0,pm0		; Processor mode bit
pm01			.btequ		1,pm0		; Processor mode bit
pm02			.btequ		2,pm0		; R/W mode select bit
pm03			.btequ		3,pm0		; Software reset bit
pm04			.btequ		4,pm0		; Multiplexed bus space select bit
pm05			.btequ		5,pm0		; Multiplexed bus space select bit
pm06			.btequ		6,pm0		; Port P4_0 to P4_3 function select bit
pm07			.btequ		7,pm0		; BCLK output disable bit
;
;-------------------------------------------------------
;	Processor mode register 1
;-------------------------------------------------------
pm1				.equ		0005h
;
pm10			.btequ		0,pm1		; CS2 area switching bit
pm11			.btequ		1,pm1		; Port P3_4 to P3_7 function select bit
pm12			.btequ		2,pm1		; Watch dog timer function select bit
pm13			.btequ		3,pm1		; Internal reserved area expansion bit
pm14			.btequ		4,pm1		; Memory area expansion bit
pm15			.btequ		5,pm1		; Memory area expansion bit
pm17			.btequ		7,pm1		; Wait bit
;
;-------------------------------------------------------
;	System clock control register 0
;-------------------------------------------------------
cm0				.equ		0006h
;
cm00			.btequ		0,cm0		; Clock output function select bit
cm01			.btequ		1,cm0		; Clock output function select bit
cm02			.btequ		2,cm0		; WAIT peripheral function clock stop bit
cm03			.btequ		3,cm0		; Xcin-Xcout drive capacity select bit
cm04			.btequ		4,cm0		; Port Xc select bit
cm05			.btequ		5,cm0		; Main clock stop bit
cm06			.btequ		6,cm0		; Main clock division select bit 0
cm07			.btequ		7,cm0		; System clock select bit
;
;-------------------------------------------------------
;	System clock control register 1
;-------------------------------------------------------
cm1				.equ		0007h
;
cm10			.btequ		0,cm1		; All clock stop control bit
cm11			.btequ		1,cm1		; System clock select bit
cm15			.btequ		5,cm1		; Xin-Xout drive capacity select bit
cm16			.btequ		6,cm1		; Main clock division select bit 1
cm17			.btequ		7,cm1		; Main clock division select bit 1
;
;-------------------------------------------------------
;	Chip select control register
;-------------------------------------------------------
csr				.equ		0008h
;
cs0				.btequ		0,csr		; CS0~ output enable bit
cs1				.btequ		1,csr		; CS1~ output enable bit
cs2				.btequ		2,csr		; CS2~ output enable bit
cs3				.btequ		3,csr		; CS3~ output enable bit
cs0w			.btequ		4,csr		; CS0~ wait bit
cs1w			.btequ		5,csr		; CS1~ wait bit
cs2w			.btequ		6,csr		; CS2~ wait bit
cs3w			.btequ		7,csr		; CS3~ wait bit
;
;-------------------------------------------------------
;	Address match interrupt enable register
;-------------------------------------------------------
aier			.equ		0009h
;
aier0			.btequ		0,aier		; Address match interrupt 0 enable bit
aier1			.btequ		1,aier		; Address match interrupt 1 enable bit
;
;-------------------------------------------------------
;	Protect register
;-------------------------------------------------------
prcr			.equ		000ah
;
prc0			.btequ		0,prcr		; Enable writting to system clock control registers 0 and 1
prc1			.btequ		1,prcr		; Enable writting to processor mode registers 0 and 1
prc2			.btequ		2,prcr		; Enable writting to port P9 direction register and SI/Oi control register(i=3,4)
prc3			.btequ		3,prcr		; Enable writting to Power supply detection register 2 and Power supply down detection register
;
;-------------------------------------------------------
;	Data bank register
;-------------------------------------------------------
dbr				 .equ		 000bh
;
ofs				 .btequ		 2,dbr		; Off set bit
bsr0			 .btequ		 3,dbr		; Bank select bit
bsr1			 .btequ		 4,dbr		; Bank select bit
bsr2			 .btequ		 5,dbr		; Bank select bit
;
;-------------------------------------------------------
;	Oscillation stop detection register
;-------------------------------------------------------
cm2				.equ		000ch
;
cm20			.btequ		0,cm2		; Oscillation stop detection bit
cm21			.btequ		1,cm2		; Main clock switch bit
cm22			.btequ		2,cm2		; Oscillation stop detection status
cm23			.btequ		3,cm2		; Clock monitor bit
cm27			.btequ		7,cm2		; Operation select bit(when an oscillation stop is detected)
;
;-------------------------------------------------------
;	Watchdog timer start register
;-------------------------------------------------------
wdts			.equ		000eh
;
;-------------------------------------------------------
;	Watchdog timer control register
;-------------------------------------------------------
wdc				.equ		000fh
;
wdc5			.btequ		5,wdc		; Cold start / warm start discrimination flag
wdc7			.btequ		7,wdc		; Prescaler select bit
;
;-------------------------------------------------------
;	Address match interrupt register 0
;-------------------------------------------------------
rmad0			.equ		0010h
rmad0l			.equ		rmad0		; Address match interrupt register 0L
rmad0m			.equ		rmad0+1		; Address match interrupt register 0M
rmad0h			.equ		rmad0+2		; Address match interrupt register 0H
;
;-------------------------------------------------------
;	Address match interrupt register 1
;-------------------------------------------------------
rmad1			.equ		0014h
rmad1l			.equ		rmad1		; Address match interrupt register 1L
rmad1m			.equ		rmad1+1		; Address match interrupt register 1M
rmad1h			.equ		rmad1+2		; Address match interrupt register 1H
;
;-------------------------------------------------------
;	Power supply detection register 1
;-------------------------------------------------------
vcr1			.equ		0019h
;
vc13			.btequ		3,vcr1		; Power supply down monitor flag
;
;-------------------------------------------------------
;	Power supply detection register 2
;-------------------------------------------------------
vcr2			.equ		001ah
;
vc25			.btequ		5,vcr2		; RAM retention limit detection monitor bit
vc26			.btequ		6,vcr2		; Reset area monitor bit
vc27			.btequ		7,vcr2		; Power supply down monitor bit
;
;-------------------------------------------------------
;	Chip select expansion control register
;-------------------------------------------------------
cse				.equ		001bh
;
cse00w			.btequ		0,cse		; CS0~ wait expansion bit
cse01w			.btequ		1,cse		; CS0~ wait expansion bit
cse10w			.btequ		2,cse		; CS1~ wait expansion bit
cse11w			.btequ		3,cse		; CS1~ wait expansion bit
cse20w			.btequ		4,cse		; CS2~ wait expansion bit
cse21w			.btequ		5,cse		; CS2~ wait expansion bit
cse30w			.btequ		6,cse		; CS3~ wait expansion bit
cse31w			.btequ		7,cse		; CS3~ wait expansion bit
;
;-------------------------------------------------------
;	PLL control register 0
;-------------------------------------------------------
plc0			.equ		001ch
;
plc00			.btequ		0,plc0		; Programmable counter select bit
plc01			.btequ		1,plc0		; Programmable counter select bit
plc02			.btequ		2,plc0		; Programmable counter select bit
plc07			.btequ		7,plc0		; Operation enable bit
;
;-------------------------------------------------------
;	Processor mode register 2
;-------------------------------------------------------
pm2				.equ		001eh
;
pm20			.btequ		0,pm2		; Specifying wait when accessing SFR at PLL operation
pm21			.btequ		1,pm2		; System clock protective bit
pm22			.btequ		2,pm2		; WDT count source protective bit
;
;-------------------------------------------------------
;	Power supply down detection register
;-------------------------------------------------------
d4int			.equ		001fh
;
d40				.btequ		0,d4int		; Power supply down detection interrupt enable bit
d41				.btequ		1,d4int		; STOP mode deactivation control bit
d42				.btequ		2,d4int		; Power supply change detection flag
d43				.btequ		3,d4int		; WDT overflow detect flag
df0				.btequ		4,d4int		; Sampling clock select bit
df1				.btequ		5,d4int		; Sampling clock select bit
;
;-------------------------------------------------------
;	DMA0 source pointer
;-------------------------------------------------------
sar0			.equ		0020h
;
sar0l			.equ		sar0		; DMA0 source pointer L
sar0m			.equ		sar0+1		; DMA0 source pointer M
sar0h			.equ		sar0+2		; DMA0 source pointer H
;
;-------------------------------------------------------
;	DMA0 destination pointer
;-------------------------------------------------------
dar0			.equ		0024h
;
dar0l			.equ		dar0		; DMA0 destination pointer L
dar0m			.equ		dar0+1		; DMA0 destination pointer M
dar0h			.equ		dar0+2		; DMA0 destination pointer H
;
;-------------------------------------------------------
;	DMA0 transfer counter
;-------------------------------------------------------
tcr0			.equ		0028h
;
tcr0l			.equ		tcr0		; DMA0 transfer counter L
tcr0h			.equ		tcr0+1		; DMA0 transfer counter H
;
;-------------------------------------------------------
;	DMA0 control register
;-------------------------------------------------------
dm0con			.equ		002ch
;
dmbit_dm0con	.btequ		0,dm0con	; Transfer unit bit select bit
dmasl_dm0con	.btequ		1,dm0con	; Repeat transfer mode select bit
dmas_dm0con		.btequ		2,dm0con	; DMA request bit
dmae_dm0con		.btequ		3,dm0con	; DMA enable bit
dsd_dm0con		.btequ		4,dm0con	; Source address direction select bit
dad_dm0con		.btequ		5,dm0con	; Destination address direction select bit
;
;-------------------------------------------------------
;	DMA1 source pointer
;-------------------------------------------------------
sar1			.equ		0030h
;
sar1l			.equ		sar1		; DMA1 source pointer L
sar1m			.equ		sar1+1		; DMA1 source pointer M
sar1h			.equ		sar1+2		; DMA1 source pointer H
;
;-------------------------------------------------------
;	DMA1 destination pointer
;-------------------------------------------------------
dar1			.equ		0034h
;
dar1l			.equ		dar1		; DMA1 destination pointer L
dar1m			.equ		dar1+1		; DMA1 destination pointer M
dar1h			.equ		dar1+2		; DMA1 destination pointer H
;
;-------------------------------------------------------
;	DMA1 transfer counter
;-------------------------------------------------------
tcr1			.equ		0038h
;
tcr1l			.equ		tcr1		; DMA1 transfer counter L
tcr1h			.equ		tcr1+1		; DMA1 transfer counter H
;
;-------------------------------------------------------
;	DMA1 control register
;-------------------------------------------------------
dm1con			.equ		003ch
;