📄 sfr62p.h
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#define inv14 invc1_addr.bit.b4 /* Output porality control bit */
#define inv15 invc1_addr.bit.b5 /* Dead time invalid bit */
#define inv16 invc1_addr.bit.b6 /* Dead time timer trigger select bit */
#define inv17 invc1_addr.bit.b7 /* Waveform reflect timing select bit */
/*------------------------------------------------------
Three-phase output buffer register 0
------------------------------------------------------*/
union byte_def idb0_addr;
#define idb0 idb0_addr.byte
#define du0 idb0_addr.bit.b0 /* U phase output buffer 0 */
#define dub0 idb0_addr.bit.b1 /* U~ phase output buffer 0 */
#define dv0 idb0_addr.bit.b2 /* V phase output buffer 0 */
#define dvb0 idb0_addr.bit.b3 /* V~ phase output buffer 0 */
#define dw0 idb0_addr.bit.b4 /* W phase output buffer 0 */
#define dwb0 idb0_addr.bit.b5 /* W~ phase output buffer 0 */
/*------------------------------------------------------
Three-phase output buffer register 1
------------------------------------------------------*/
union byte_def idb1_addr;
#define idb1 idb1_addr.byte
#define du1 idb1_addr.bit.b0 /* U phase output buffer 1 */
#define dub1 idb1_addr.bit.b1 /* U~ phase output buffer 1 */
#define dv1 idb1_addr.bit.b2 /* V phase output buffer 1 */
#define dvb1 idb1_addr.bit.b3 /* V~ phase output buffer 1 */
#define dw1 idb1_addr.bit.b4 /* W phase output buffer 1 */
#define dwb1 idb1_addr.bit.b5 /* W~ phase output buffer 1 */
/*------------------------------------------------------
Dead time timer ; Use "MOV" instruction when writing to this register.
------------------------------------------------------*/
union byte_def dtt_addr;
#define dtt dtt_addr.byte
/*------------------------------------------------------------------
Timer B2 interrupt occurrences frequency set counter ; Use "MOV" instruction when writing to this register.
-------------------------------------------------------------------*/
union byte_def ictb2_addr;
#define ictb2 ictb2_addr.byte
/*------------------------------------------------------
Timer B3 mode register
------------------------------------------------------*/
union byte_def tb3mr_addr;
#define tb3mr tb3mr_addr.byte
#define tmod0_tb3mr tb3mr_addr.bit.b0 /* Operation mode select bit */
#define tmod1_tb3mr tb3mr_addr.bit.b1 /* Operation mode select bit */
#define mr0_tb3mr tb3mr_addr.bit.b2
#define mr1_tb3mr tb3mr_addr.bit.b3
#define mr2_tb3mr tb3mr_addr.bit.b4
#define mr3_tb3mr tb3mr_addr.bit.b5
#define tck0_tb3mr tb3mr_addr.bit.b6 /* Count source select bit */
#define tck1_tb3mr tb3mr_addr.bit.b7 /* Count source select bit */
/*------------------------------------------------------
Timer B4 mode register
------------------------------------------------------*/
union byte_def tb4mr_addr;
#define tb4mr tb4mr_addr.byte
#define tmod0_tb4mr tb4mr_addr.bit.b0 /* Operation mode select bit */
#define tmod1_tb4mr tb4mr_addr.bit.b1 /* Operation mode select bit */
#define mr0_tb4mr tb4mr_addr.bit.b2
#define mr1_tb4mr tb4mr_addr.bit.b3
#define mr3_tb4mr tb4mr_addr.bit.b5
#define tck0_tb4mr tb4mr_addr.bit.b6 /* Count source select bit */
#define tck1_tb4mr tb4mr_addr.bit.b7 /* Count source select bit */
/*------------------------------------------------------
Timer B5 mode register
------------------------------------------------------*/
union byte_def tb5mr_addr;
#define tb5mr tb5mr_addr.byte
#define tmod0_tb5mr tb5mr_addr.bit.b0 /* Operation mode select bit */
#define tmod1_tb5mr tb5mr_addr.bit.b1 /* Operation mode select bit */
#define mr0_tb5mr tb5mr_addr.bit.b2
#define mr1_tb5mr tb5mr_addr.bit.b3
#define mr3_tb5mr tb5mr_addr.bit.b5
#define tck0_tb5mr tb5mr_addr.bit.b6 /* Count source select bit */
#define tck1_tb5mr tb5mr_addr.bit.b7 /* Count source select bit */
/*------------------------------------------------------
Interrupt request cause select register 2
------------------------------------------------------*/
union byte_def ifsr2a_addr;
#define ifsr2a ifsr2a_addr.byte
#define ifsr26 ifsr2a_addr.bit.b6 /* Interrupt request cause select bit */
#define ifsr27 ifsr2a_addr.bit.b7 /* Interrupt request cause select bit */
/*------------------------------------------------------
Interrupt request cause select register
------------------------------------------------------*/
union byte_def ifsr_addr;
#define ifsr ifsr_addr.byte
#define ifsr0 ifsr_addr.bit.b0 /* INT0~ interrupt polarity switching bit */
#define ifsr1 ifsr_addr.bit.b1 /* INT1~ interrupt polarity switching bit */
#define ifsr2 ifsr_addr.bit.b2 /* INT2~ interrupt polarity switching bit */
#define ifsr3 ifsr_addr.bit.b3 /* INT3~ interrupt polarity switching bit */
#define ifsr4 ifsr_addr.bit.b4 /* INT4~ interrupt polarity switching bit */
#define ifsr5 ifsr_addr.bit.b5 /* INT5~ interrupt polarity switching bit */
#define ifsr6 ifsr_addr.bit.b6 /* Interrupt request cause select bit */
#define ifsr7 ifsr_addr.bit.b7 /* Interrupt request cause select bit */
/*------------------------------------------------------
SI/O3 transmit/receive register
------------------------------------------------------*/
union byte_def s3trr_addr;
#define s3trr s3trr_addr.byte
/*------------------------------------------------------
SI/O3 control register
------------------------------------------------------*/
union byte_def s3c_addr;
#define s3c s3c_addr.byte
#define sm30 s3c_addr.bit.b0 /* Internal synchronous clock select bit */
#define sm31 s3c_addr.bit.b1 /* Internal synchronous clock select bit */
#define sm32 s3c_addr.bit.b2 /* Sout3 output disable bit */
#define sm33 s3c_addr.bit.b3 /* SI/O3 port select bit */
#define sm34 s3c_addr.bit.b4 /* CLK polarity select bit */
#define sm35 s3c_addr.bit.b5 /* Transfer direction select bit */
#define sm36 s3c_addr.bit.b6 /* Synchronous clock select bit */
#define sm37 s3c_addr.bit.b7 /* Sout3 initial value set bit */
/*------------------------------------------------------
SI/O3 bit rate generator ; Use "MOV" instruction when writing to this register.
------------------------------------------------------*/
union byte_def s3brg_addr;
#define s3brg s3brg_addr.byte
/*------------------------------------------------------
SI/O4 transmit/receive register
------------------------------------------------------*/
union byte_def s4trr_addr;
#define s4trr s4trr_addr.byte
/*------------------------------------------------------
SI/O4 control register
------------------------------------------------------*/
union byte_def s4c_addr;
#define s4c s4c_addr.byte
#define sm40 s4c_addr.bit.b0 /* Internal synchronous clock select bit */
#define sm41 s4c_addr.bit.b1 /* Internal synchronous clock select bit */
#define sm42 s4c_addr.bit.b2 /* Sout4 output disable bit */
#define sm43 s4c_addr.bit.b3 /* SI/O4 port select bit */
#define sm44 s4c_addr.bit.b4 /* CLK polarity select bit */
#define sm45 s4c_addr.bit.b5 /* Transfer direction select bit */
#define sm46 s4c_addr.bit.b6 /* Synchronous clock select bit */
#define sm47 s4c_addr.bit.b7 /* Sout4 initial value set bit */
/*------------------------------------------------------
SI/O4 bit rate generator ; Use "MOV" instruction when writing to this register.
------------------------------------------------------*/
union byte_def s4brg_addr;
#define s4brg s4brg_addr.byte
/*------------------------------------------------------
UART0 special mode register 4
------------------------------------------------------*/
union byte_def u0smr4_addr;
#define u0smr4 u0smr4_addr.byte
#define stareq_u0smr4 u0smr4_addr.bit.b0 /* Start condition generate bit */
#define rstareq_u0smr4 u0smr4_addr.bit.b1 /* Restart condition generate bit */
#define stpreq_u0smr4 u0smr4_addr.bit.b2 /* Stop condition generate bit */
#define stspsel_u0smr4 u0smr4_addr.bit.b3 /* SCL,SDA output select bit */
#define ackd_u0smr4 u0smr4_addr.bit.b4 /* ACK data bit */
#define ackc_u0smr4 u0smr4_addr.bit.b5 /* ACK data output enable bit */
#define sclhi_u0smr4 u0smr4_addr.bit.b6 /* SCL output stop enable bit */
#define swc9_u0smr4 u0smr4_addr.bit.b7 /* Final bit L hold enable bit */
/*------------------------------------------------------
UART0 special mode register 3
------------------------------------------------------*/
union byte_def u0smr3_addr;
#define u0smr3 u0smr3_addr.byte
#define ckph_u0smr3 u0smr3_addr.bit.b1 /* Clock phase set bit */
#define nodc_u0smr3 u0smr3_addr.bit.b3 /* Clock output set bit */
#define dl0_u0smr3 u0smr3_addr.bit.b5 /* SDA0(TxD0) digital delay setup bit */
#define dl1_u0smr3 u0smr3_addr.bit.b6 /* SDA0(TxD0) digital delay setup bit */
#define dl2_u0smr3 u0smr3_addr.bit.b7 /* SDA0(TxD0) digital delay setup bit */
/*------------------------------------------------------
UART0 special mode register 2
------------------------------------------------------*/
union byte_def u0smr2_addr;
#define u0smr2 u0smr2_addr.byte
#define iicm2_u0smr2 u0smr2_addr.bit.b0 /* IIC mode selection bit 2 */
#define csc_u0smr2 u0smr2_addr.bit.b1 /* Clock-synchronous bit */
#define swc_u0smr2 u0smr2_addr.bit.b2 /* SCL wait output bit */
#define als_u0smr2 u0smr2_addr.bit.b3 /* SDA output stop bit */
#define stac_u0smr2 u0smr2_addr.bit.b4 /* UART0 initialization bit */
#define swc2_u0smr2 u0smr2_addr.bit.b5 /* SCL wait output bit 2 */
#define sdhi_u0smr2 u0smr2_addr.bit.b6 /* SDA output disable bit */
/*------------------------------------------------------
UART0 special mode register
------------------------------------------------------*/
union byte_def u0smr_addr;
#define u0smr u0smr_addr.byte
#define iicm_u0smr u0smr_addr.bit.b0 /* IIC mode selection bit */
#define abc_u0smr u0smr_addr.bit.b1 /* Arbitration lost detecting flag control bit */
#define bbs_u0smr u0smr_addr.bit.b2 /* Bus busy flag */
#define lsyn_u0smr u0smr_addr.bit.b3 /* SCLL sync output enable bit */
#define abscs_u0smr u0smr_addr.bit.b4 /* Bus collision detect sampling clock select bit */
#define acse_u0smr u0smr_addr.bit.b5 /* Auto clear function select bit of transmit enable bit */
#define sss_u0smr u0smr_addr.bit.b6 /* Transmit start condition select bit */
/*------------------------------------------------------
UART1 special mode register 4
------------------------------------------------------*/
union byte_def u1smr4_addr;
#define u1smr4 u1smr4_addr.byte
#define stareq_u1smr4 u1smr4_addr.bit.b0 /* Start condition generate bit */
#define rstareq_u1smr4 u1smr4_addr.bit.b1 /* Restart condition generate bit */
#define stpreq_u1smr4 u1smr4_addr.bit.b2 /* Stop condition generate bit */
#define stspsel_u1smr4 u1smr4_addr.bit.b3 /* SCL,SDA output select bit */
#define ackd_u1smr4 u1smr4_addr.bit.b4 /* ACK data bit */
#define ackc_u1smr4 u1smr4_addr.bit.b5 /* ACK data output enable bit */
#define sclhi_u1smr4 u1smr4_addr.bit.b6 /* SCL output stop enable bit */
#define swc9_u1smr4 u1smr4_addr.bit.b7 /* Final bit L hold enable bit */
/*------------------------------------------------------
UART1 special mode register 3
------------------------------------------------------*/
union byte_def u1smr3_addr;
#define u1smr3 u1smr3_addr.byte
#define ckph_u1smr3 u1smr3_addr.bit.b1 /* Clock phase set bit */
#define nodc_u1smr3 u1smr3_addr.bit.b3 /* Clock output set bit */
#define dl0_u1smr3 u1smr3_addr.bit.b5 /* SDA1(TxD1) digital delay setup bit */
#define dl1_u1smr3 u1smr3_addr.bit.b6 /* SDA1(TxD1) digital delay setup bit */
#define dl2_u1smr3 u1smr3_addr.bit.b7 /* SDA1(TxD1) digital delay setup bit */
/*------------------------------------------------------
UART1 special mode register 2
------------------------------------------------------*/
union byte_def u1smr2_addr;
#define u1smr2 u1smr2_addr.byte
#define iicm2_u1smr2 u1smr2_addr.bit.b0 /* IIC mode selection bit 2 */
#define csc_u1smr2 u1smr2_addr.bit.b1 /* Clock-synchronous bit */
#define swc_u1smr2 u1smr2_addr.bit.b2 /* SCL wait output bit */
#define als_u1smr2 u1smr2_addr.bit.b3 /* SDA output stop bit */
#define stac_u1smr2 u1smr2_addr.bit.b4 /* UART0 initialization bit */
#define swc2_u1smr2 u1smr2_addr.bit.b5 /* SCL wait output bit 2 */
#define sdhi_u1smr2 u1smr2_addr.bit.b6 /* SDA output disable bit */
/*------------------------------------------------------
UART1 special mode register
------------------------------------------------------*/
union byte_def u1smr_addr;
#define u1smr u1smr_addr.byte
#define iicm_u1smr u1smr_addr.bit.b0 /* IIC mode selection bit */
#define abc_u1smr u1smr_addr.bit.b1 /* Arbitration lost detecting flag control bit */
#define bbs_u1smr u1smr_addr.bit.b2 /* Bus busy flag */
#define lsyn_u1smr u1smr_addr.bit.b3 /* SCLL sync output enable bit */
#define abscs_u1smr u1smr_addr.bit.b4 /* Bus collision detect sampling clock select bit */
#define acse_u1smr u1smr_addr.bit.b5 /* Auto clear function select bit of transmit enable bit */
#define sss_u1smr u1smr_addr.bit.b6 /* Transmit start condition select bit */
/*------------------------------------------------------
UART2 special mode register 4
------------------------------------------------------*/
union byte_def u2smr4_addr;
#define u2smr4 u2smr4_addr.byte
#define stareq_u2smr4 u2smr4_addr.bit.b0 /* Start condition generate bit */
#define rstareq_u2smr4 u2smr4_addr.bit.b1 /* Restart condition generate bit */
#define stpreq_u2smr4 u2smr4_addr.bit.b2 /* Stop condition generate bit */
#define stspsel_u2smr4 u2smr4_addr.bit.b3 /* SCL,SDA output select bit */
#define ackd_u2smr4 u2smr4_addr.bit.b4 /* ACK data bit */
#define ackc_u2smr4 u2smr4_addr.bit.b5 /* ACK data output enable bit */
#define sclhi_u2smr4 u2smr4_addr.bit.b6 /* SCL output stop enable bit */
#define swc9_u2smr4 u2smr4_addr.bit.b7 /* Final bit L hold enable bit */
/*------------------------------------------------------
UART2 special mode register 3
------------------------------------------------------*/
union byte_def u2smr3_addr;
#define u2smr3 u2smr3_addr.byte
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