📄 sfr62p.h
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------------------------------------------------------*/
union byte_def aier_addr;
#define aier aier_addr.byte
#define aier0 aier_addr.bit.b0 /* Address match interrupt 0 enable bit */
#define aier1 aier_addr.bit.b1 /* Address match interrupt 1 enable bit */
/*------------------------------------------------------
Protect register
------------------------------------------------------*/
union byte_def prcr_addr;
#define prcr prcr_addr.byte
#define prc0 prcr_addr.bit.b0 /* Enable writting to system clock control registers 0 and 1 */
#define prc1 prcr_addr.bit.b1 /* Enable writting to processor mode registers 0 and 1 */
#define prc2 prcr_addr.bit.b2 /* Enable writting to port P9 direction register and SI/Oi control register(i=3,4) */
#define prc3 prcr_addr.bit.b3 /* Enable writting to Power supply detection register 2 and Power supply down detection register */
/*------------------------------------------------------
Data bank register
------------------------------------------------------*/
union byte_def dbr_addr;
#define dbr dbr_addr.byte
#define ofs dbr_addr.bit.b2 /* Offset bit */
#define bsr0 dbr_addr.bit.b3 /* Bank select bit 0 */
#define bsr1 dbr_addr.bit.b4 /* Bank select bit 1 */
#define bsr2 dbr_addr.bit.b5 /* Bank select bit 2 */
/*------------------------------------------------------
Oscillation stop detection register
------------------------------------------------------*/
union byte_def cm2_addr;
#define cm2 cm2_addr.byte
#define cm20 cm2_addr.bit.b0 /* Oscillation stop detection bit */
#define cm21 cm2_addr.bit.b1 /* Main clock switch bit */
#define cm22 cm2_addr.bit.b2 /* Oscillation stop detection status */
#define cm23 cm2_addr.bit.b3 /* Clock monitor bit */
#define cm27 cm2_addr.bit.b7 /* Operation select bit(when an oscillation stop is detected) */
/*------------------------------------------------------
Watchdog timer start register
------------------------------------------------------*/
union byte_def wdts_addr;
#define wdts wdts_addr.byte
/*------------------------------------------------------
Watchdog timer control register
------------------------------------------------------*/
union byte_def wdc_addr;
#define wdc wdc_addr.byte
#define wdc5 wdc_addr.bit.b5 /* Cold start / warm start discrimination flag */
#define wdc7 wdc_addr.bit.b7 /* Prescaler select bit */
/*------------------------------------------------------
Power supply detection register 1
------------------------------------------------------*/
union byte_def vcr1_addr;
#define vcr1 vcr1_addr.byte
#define vc13 vcr1_addr.bit.b3 /* Power supply down monitor flag */
/*------------------------------------------------------
Power supply detection register 2
------------------------------------------------------*/
union byte_def vcr2_addr;
#define vcr2 vcr2_addr.byte
#define vc25 vcr2_addr.bit.b5 /* RAM retention limit detection monitor bit */
#define vc26 vcr2_addr.bit.b6 /* Reset area monitor bit */
#define vc27 vcr2_addr.bit.b7 /* Power supply down monitor bit */
/*------------------------------------------------------
Chip select expansion control register
------------------------------------------------------*/
union byte_def cse_addr;
#define cse cse_addr.byte
#define cse00w cse_addr.bit.b0 /* CS0~ wait expansion bit */
#define cse01w cse_addr.bit.b1 /* CS0~ wait expansion bit */
#define cse10w cse_addr.bit.b2 /* CS1~ wait expansion bit */
#define cse11w cse_addr.bit.b3 /* CS1~ wait expansion bit */
#define cse20w cse_addr.bit.b4 /* CS2~ wait expansion bit */
#define cse21w cse_addr.bit.b5 /* CS2~ wait expansion bit */
#define cse30w cse_addr.bit.b6 /* CS3~ wait expansion bit */
#define cse31w cse_addr.bit.b7 /* CS3~ wait expansion bit */
/*------------------------------------------------------
PLL control register 0
------------------------------------------------------*/
union byte_def plc0_addr;
#define plc0 plc0_addr.byte
#define plc00 plc0_addr.bit.b0 /* Programmable counter select bit */
#define plc01 plc0_addr.bit.b1 /* Programmable counter select bit */
#define plc02 plc0_addr.bit.b2 /* Programmable counter select bit */
#define plc07 plc0_addr.bit.b7 /* Operation enable bit */
/*------------------------------------------------------
Processor mode register 2
------------------------------------------------------*/
union byte_def pm2_addr;
#define pm2 pm2_addr.byte
#define pm20 pm2_addr.bit.b0 /* Specifying wait when accessing SFR at PLL operation */
#define pm21 pm2_addr.bit.b1 /* System clock protective bit */
#define pm22 pm2_addr.bit.b2 /* WDT count source protective bit */
/*------------------------------------------------------
Power supply down detection register
------------------------------------------------------*/
union byte_def d4int_addr;
#define d4int d4int_addr.byte
#define d40 d4int_addr.bit.b0 /* Power supply down detection interrupt enable bit */
#define d41 d4int_addr.bit.b1 /* STOP mode deactivation control bit */
#define d42 d4int_addr.bit.b2 /* Power supply change detection flag */
#define d43 d4int_addr.bit.b3 /* WDT overflow detect flag */
#define df0 d4int_addr.bit.b4 /* Sampling clock select bit */
#define df1 d4int_addr.bit.b5 /* Sampling clock select bit */
/*------------------------------------------------------
DMA0 control register
------------------------------------------------------*/
union byte_def dm0con_addr;
#define dm0con dm0con_addr.byte
#define dmbit_dm0con dm0con_addr.bit.b0 /* Transfer unit bit select bit */
#define dmasl_dm0con dm0con_addr.bit.b1 /* Repeat transfer mode select bit */
#define dmas_dm0con dm0con_addr.bit.b2 /* DMA request bit */
#define dmae_dm0con dm0con_addr.bit.b3 /* DMA enable bit */
#define dsd_dm0con dm0con_addr.bit.b4 /* Source address direction select bit */
#define dad_dm0con dm0con_addr.bit.b5 /* Destination address direction select bit */
/*------------------------------------------------------
DMA1 control register
------------------------------------------------------*/
union byte_def dm1con_addr;
#define dm1con dm1con_addr.byte
#define dmbit_dm1con dm1con_addr.bit.b0 /* Transfer unit bit select bit */
#define dmasl_dm1con dm1con_addr.bit.b1 /* Repeat transfer mode select bit */
#define dmas_dm1con dm1con_addr.bit.b2 /* DMA request bit */
#define dmae_dm1con dm1con_addr.bit.b3 /* DMA enable bit */
#define dsd_dm1con dm1con_addr.bit.b4 /* Source address direction select bit */
#define dad_dm1con dm1con_addr.bit.b5 /* Destination address direction select bit */
/*------------------------------------------------------
INT3 interrupt control register
------------------------------------------------------*/
union byte_def int3ic_addr;
#define int3ic int3ic_addr.byte
#define ilvl0_int3ic int3ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_int3ic int3ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_int3ic int3ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_int3ic int3ic_addr.bit.b3 /* Interrupt request bit */
#define pol_int3ic int3ic_addr.bit.b4 /* Polarity select bit */
/*------------------------------------------------------
Timer B5 interrupt control register
------------------------------------------------------*/
union byte_def tb5ic_addr;
#define tb5ic tb5ic_addr.byte
#define ilvl0_tb5ic tb5ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_tb5ic tb5ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_tb5ic tb5ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_tb5ic tb5ic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
Timer B4 interrupt control register
------------------------------------------------------*/
union byte_def tb4ic_addr;
#define tb4ic tb4ic_addr.byte
#define ilvl0_tb4ic tb4ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_tb4ic tb4ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_tb4ic tb4ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_tb4ic tb4ic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
Timer B3 interrupt control register
------------------------------------------------------*/
union byte_def tb3ic_addr;
#define tb3ic tb3ic_addr.byte
#define ilvl0_tb3ic tb3ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_tb3ic tb3ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_tb3ic tb3ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_tb3ic tb3ic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
UART1 BUS collision detection interrupt control register
------------------------------------------------------*/
union byte_def u1bcnic_addr;
#define u1bcnic u1bcnic_addr.byte
#define ilvl0_u1bcnic u1bcnic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_u1bcnic u1bcnic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_u1bcnic u1bcnic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_u1bcnic u1bcnic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
UART0 BUS collision detection interrupt control register
------------------------------------------------------*/
union byte_def u0bcnic_addr;
#define u0bcnic u0bcnic_addr.byte
#define ilvl0_u0bcnic u0bcnic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_u0bcnic u0bcnic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_u0bcnic u0bcnic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_u0bcnic u0bcnic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
SI/O4 interrupt control register
------------------------------------------------------*/
union byte_def s4ic_addr;
#define s4ic s4ic_addr.byte
#define ilvl0_s4ic s4ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_s4ic s4ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_s4ic s4ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_s4ic s4ic_addr.bit.b3 /* Interrupt request bit */
#define pol_s4ic s4ic_addr.bit.b4 /* Polarity select bit */
/*------------------------------------------------------
SI/O3 interrupt control register
------------------------------------------------------*/
union byte_def s3ic_addr;
#define s3ic s3ic_addr.byte
#define ilvl0_s3ic s3ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_s3ic s3ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_s3ic s3ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_s3ic s3ic_addr.bit.b3 /* Interrupt request bit */
#define pol_s3ic s3ic_addr.bit.b4 /* Polarity select bit */
/*------------------------------------------------------
INT5 interrupt control register
------------------------------------------------------*/
union byte_def int5ic_addr;
#define int5ic int5ic_addr.byte
#define ilvl0_int5ic int5ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_int5ic int5ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_int5ic int5ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_int5ic int5ic_addr.bit.b3 /* Interrupt request bit */
#define pol_int5ic int5ic_addr.bit.b4 /* Polarity select bit */
/*------------------------------------------------------
INT4 interrupt control register
------------------------------------------------------*/
union byte_def int4ic_addr;
#define int4ic int4ic_addr.byte
#define ilvl0_int4ic int4ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_int4ic int4ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_int4ic int4ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_int4ic int4ic_addr.bit.b3 /* Interrupt request bit */
#define pol_int4ic int4ic_addr.bit.b4 /* Polarity select bit */
/*------------------------------------------------------
UART2 BUS collision detection interrupt control register
------------------------------------------------------*/
union byte_def bcnic_addr;
#define bcnic bcnic_addr.byte
#define ilvl0_bcnic bcnic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_bcnic bcnic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_bcnic bcnic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_bcnic bcnic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
DMA0 interrupt control register
------------------------------------------------------*/
union byte_def dm0ic_addr;
#define dm0ic dm0ic_addr.byte
#define ilvl0_dm0ic dm0ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_dm0ic dm0ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_dm0ic dm0ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_dm0ic dm0ic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
DMA1 interrupt control register
------------------------------------------------------*/
union byte_def dm1ic_addr;
#define dm1ic dm1ic_addr.byte
#define ilvl0_dm1ic dm1ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_dm1ic dm1ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_dm1ic dm1ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_dm1ic dm1ic_addr.bit.b3 /* Interrupt request bit */
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