📄 sfr62_ass.inc
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;************************************************************************************
;* *
;* file name : definition of M16C/62's SFR *
;* *
;* Copyright : MITSUBISHI ELECTRIC CORPORATION *
;* *
;* Version : 1.00 ( 1997- 6- 9 ) *
;* : 1.01 ( 1998-11-13 ) *
;* flash control register 03b7h add *
;* UART2 Special mode register2 0376h add *
;* pm1 add pm13 *
;* u2smr modify iicm *
;* u0rb,u1rb,u2rb add abt *
;* dm0sl,dm1sl add dms *
;* : 1.02 ( 1999-01-08 ) *
;* fer -> fmcr modify *
;* : 1.03 ( 1999-08-24 ) *
;* fmcr -> fmr0 modify *
;* fmr0 add fmr05 *
;* flash memory control register 1 ( fmr1 ) 03b6h add *
;* fmr1 add fmr13 *
;* : 1.04 ( 2000-03-24 ) *
;* UART2 Special mode register3 ( u2smr3 ) 0375h add *
;* idb1 .equ 034bh *
;* du1 .btequ 0,idb0 -> 0,idb1 modify *
;* dub1 .btequ 1,idb1 *
;* u2smr 0377h add sdds_u2smr(SDA digital delay select bit) *
;************************************************************************************
;
; note:
; This data is a freeware that SFR for M16C/62 and is described.
; Mitsubishi Electric Corporation assumes no responsibility for any damage
; that occurred by this data.
;
;-------------------------------------------------------
; Processor mode register 0
;-------------------------------------------------------
pm0 .equ 0004h
;
pm00 .btequ 0,pm0 ; Processor mode bit
pm01 .btequ 1,pm0 ; Processor mode bit
pm02 .btequ 2,pm0 ; R/W mode select bit
pm03 .btequ 3,pm0 ; Software reset bit
pm04 .btequ 4,pm0 ; Multiplexed bus space select bit
pm05 .btequ 5,pm0 ; Multiplexed bus space select bit
pm06 .btequ 6,pm0 ; Port P40 to P43 function select bit
pm07 .btequ 7,pm0 ; BCLK output disable bit
;
;-------------------------------------------------------
; Processor mode register 1
;-------------------------------------------------------
pm1 .equ 0005h
;
pm13 .btequ 3,pm1 ;
pm14 .btequ 4,pm1 ;
pm15 .btequ 5,pm1 ;
pm16 .btequ 6,pm1 ; Reserved bit
pm17 .btequ 7,pm1 ; Wait bit
;
;-------------------------------------------------------
; System clock control register 0
;-------------------------------------------------------
cm0 .equ 0006h
;
cm00 .btequ 0,cm0 ; Clock output function select bit
cm01 .btequ 1,cm0 ; Clock output function select bit
cm02 .btequ 2,cm0 ; WAIT peripheral function Clock stop bit
cm03 .btequ 3,cm0 ; Xcin-Xcout drive capacity select bit
cm04 .btequ 4,cm0 ; Port Xc select bit
cm05 .btequ 5,cm0 ; Main Clock stop bit
cm06 .btequ 6,cm0 ; Main Clock division selectbit0
cm07 .btequ 7,cm0 ; System clock select bit
;
;-------------------------------------------------------
; System clock control register 1
;-------------------------------------------------------
cm1 .equ 0007h
;
cm10 .btequ 0,cm1 ; All clock stop control bit
cm15 .btequ 5,cm1 ; Xin-Xout drive capacity select bit
cm16 .btequ 6,cm1 ; Main Clock division select bit
cm17 .btequ 7,cm1 ; Main Clock division select bit
;
;-------------------------------------------------------
; Chip select control register
;-------------------------------------------------------
csr .equ 0008h
;
cs0 .btequ 0,csr ; CS0 output enable bit
cs1 .btequ 1,csr ; CS1 output enable bit
cs2 .btequ 2,csr ; CS2 output enable bit
cs3 .btequ 3,csr ; CS3 output enable bit
cs0w .btequ 4,csr ; CS0 wait bit
cs1w .btequ 5,csr ; CS1 wait bit
cs2w .btequ 6,csr ; CS2 wait bit
cs3w .btequ 7,csr ; CS3 wait bit
;
;-------------------------------------------------------
; Address match interrupt enable register
;-------------------------------------------------------
aier .equ 0009h
;
aier0 .btequ 0,aier ; Address match interrupt 0 enable bit
aier1 .btequ 1,aier ; Address match interrupt 1 enable bit
;
;-------------------------------------------------------
; Protect register
;-------------------------------------------------------
prcr .equ 000ah
;
prc0 .btequ 0,prcr ; Enable writting to system clock control register
prc1 .btequ 1,prcr ; Enable writting to processor mode register
prc2 .btequ 2,prcr ; Enable writting to port P9 direction register
;
;-------------------------------------------------------
; Data bank register
;-------------------------------------------------------
dbr .equ 000bh
;
ofs .btequ 2,dbr
bsr0 .btequ 3,dbr
bsr1 .btequ 4,dbr
bsr2 .btequ 5,dbr
;
;-------------------------------------------------------
; Watchdog timer
;-------------------------------------------------------
wdts .equ 000eh ; Watchdog timer start register
;
wdc .equ 000fh ; Watchdog timer control register
;
wdc7 .btequ 7,wdc ; Prescaler select bit
;
;-------------------------------------------------------
; Address match interrupt register 0
;-------------------------------------------------------
rmad0 .equ 0010h
rmad0l .equ rmad0 ; Address match interrupt register 0L
rmad0m .equ rmad0+1 ; Address match interrupt register 0M
rmad0h .equ rmad0+2 ; Address match interrupt register 0H
;
;-------------------------------------------------------
; Address match interrupt register 1
;-------------------------------------------------------
rmad1 .equ 0014h
rmad1l .equ rmad1 ; Address match interrupt register 1L
rmad1m .equ rmad1+1 ; Address match interrupt register 1M
rmad1h .equ rmad1+2 ; Address match interrupt register 1H
;
;-------------------------------------------------------
; DMA0 source pointer
;-------------------------------------------------------
sar0 .equ 0020h
sar0l .equ sar0 ; DMA0 source pointer L
sar0m .equ sar0+1 ; DMA0 source pointer M
sar0h .equ sar0+2 ; DMA0 source pointer H
;
;-------------------------------------------------------
; DMA0 destination pointer
;-------------------------------------------------------
dar0 .equ 0024h
dar0l .equ dar0 ; DMA0 destination pointer L
dar0m .equ dar0+1 ; DMA0 destination pointer M
dar0h .equ dar0+2 ; DMA0 destination pointer H
;
;-------------------------------------------------------
; DMA0 transfer counter
;-------------------------------------------------------
tcr0 .equ 0028h
tcr0l .equ tcr0 ; DMA0 transfer counter L
tcr0h .equ tcr0+1 ; DMA0 transfer counter H
;
;-------------------------------------------------------
; DMA0 control register
;-------------------------------------------------------
dm0con .equ 002ch
;
dmbit_dm0con .btequ 0,dm0con ; Transfer unit bit select bit
dmasl_dm0con .btequ 1,dm0con ; Repeat transfer mode select bit
dmas_dm0con .btequ 2,dm0con ; DMA request bit
dmae_dm0con .btequ 3,dm0con ; DMA enable bit
dsd_dm0con .btequ 4,dm0con ; Source address direction select bit
dad_dm0con .btequ 5,dm0con ; Destination address direction select bit
;
;-------------------------------------------------------
; DMA1 source pointer
;-------------------------------------------------------
sar1 .equ 0030h
sar1l .equ sar1 ; DMA1 source pointer L
sar1m .equ sar1+1 ; DMA1 source pointer M
sar1h .equ sar1+2 ; DMA1 source pointer H
;
;-------------------------------------------------------
; DMA1 destination pointer
;-------------------------------------------------------
dar1 .equ 0034h
dar1l .equ dar1 ; DMA1 destination pointer L
dar1m .equ dar1+1 ; DMA1 destination pointer M
dar1h .equ dar1+2 ; DMA1 destination pointer H
;
;-------------------------------------------------------
; DMA1 transfer counter
;-------------------------------------------------------
tcr1 .equ 0038h
tcr1l .equ tcr1 ;DMA1 transfer counter L
tcr1h .equ tcr1+1 ;DMA1 transfer counter H
;
;-------------------------------------------------------
; DMA1 control register
;-------------------------------------------------------
dm1con .equ 003ch
;
dmbit_dm1con .btequ 0,dm1con ; Transfer unit bit select bit
dmasl_dm1con .btequ 1,dm1con ; Repeat transfer mode select bit
dmas_dm1con .btequ 2,dm1con ; DMA request bit
dmae_dm1con .btequ 3,dm1con ; DMA disable bit
dsd_dm1con .btequ 4,dm1con ; Source address direction select bit
dad_dm1con .btequ 5,dm1con ; Destination address direction select bit
;
;-------------------------------------------------------
; Interrupt control register
;-------------------------------------------------------
int3ic .equ 0044h ; INT3
ilvl0_int3ic .btequ 0,int3ic ; Interrupt priority level select bit
ilvl1_int3ic .btequ 1,int3ic ;
ilvl2_int3ic .btequ 2,int3ic ;
ir_int3ic .btequ 3,int3ic ; Interrupt request bit
pol_int3ic .btequ 4,int3ic ; Polarity select bit
;
tb5ic .equ 0045h ; TimerB5
ilvl0_tb5ic .btequ 0,tb5ic ; Interrupt priority level select bit
ilvl1_tb5ic .btequ 1,tb5ic ;
ilvl2_tb5ic .btequ 2,tb5ic ;
ir_tb5ic .btequ 3,tb5ic ; Interrupt request bit
;
tb4ic .equ 0046h ; TimerB4
ilvl0_tb4ic .btequ 0,tb4ic ; Interrupt priority level select bit
ilvl1_tb4ic .btequ 1,tb4ic ;
ilvl2_tb4ic .btequ 2,tb4ic ;
ir_tb4ic .btequ 3,tb4ic ; Interrupt request bit
;
tb3ic .equ 0047h ; TimerB3
ilvl0_tb3ic .btequ 0,tb3ic ; Interrupt priority level select bit
ilvl1_tb3ic .btequ 1,tb3ic ;
ilvl2_tb3ic .btequ 2,tb3ic ;
ir_tb3ic .btequ 3,tb3ic ; Interrupt request bit
;
s4ic .equ 0048h ; SI/O4
ilvl0_s4ic .btequ 0,s4ic ; Interrupt priority level select bit
ilvl1_s4ic .btequ 1,s4ic ;
ilvl2_s4ic .btequ 2,s4ic ;
ir_s4ic .btequ 3,s4ic ; Interrupt request bit
pol_s4ic .btequ 4,s4ic ; Polarity select bit
;
s3ic .equ 0049h ; SI/O3
ilvl0_s3ic .btequ 0,s3ic ; Interrupt priority level select bit
ilvl1_s3ic .btequ 1,s3ic ;
ilvl2_s3ic .btequ 2,s3ic ;
ir_s3ic .btequ 3,s3ic ; Interrupt request bit
pol_s3ic .btequ 4,s3ic ; Polarity select bit
;
int5ic .equ 0048h ; INT5
ilvl0_int5ic .btequ 0,int5ic ; Interrupt priority level select bit
ilvl1_int5ic .btequ 1,int5ic ;
ilvl2_int5ic .btequ 2,int5ic ;
ir_int5ic .btequ 3,int5ic ; Interrupt request bit
pol_int5ic .btequ 4,int5ic ; Polarity select bit
;
int4ic .equ 0049h ; INT4
ilvl0_int4ic .btequ 0,int4ic ; Interrupt priority level select bit
ilvl1_int4ic .btequ 1,int4ic ;
ilvl2_int4ic .btequ 2,int4ic ;
ir_int4ic .btequ 3,int4ic ; Interrupt request bit
pol_int4ic .btequ 4,int4ic ; Polarity select bit
;
bcnic .equ 004ah ; Bus collision detection interrupt control register
ilvl0_bcnic .btequ 0,bcnic ; Interrupt priority level select bit
ilvl1_bcnic .btequ 1,bcnic ;
ilvl2_bcnic .btequ 2,bcnic ;
ir_bcnic .btequ 3,bcnic ; Interrupt request bit
;
dm0ic .equ 004bh ; DMA0 interrupt control register
ilvl0_dm0ic .btequ 0,dm0ic ; Interrupt priority level select bit
ilvl1_dm0ic .btequ 1,dm0ic ;
ilvl2_dm0ic .btequ 2,dm0ic ;
ir_dm0ic .btequ 3,dm0ic ; Interrupt request bit
;
dm1ic .equ 004ch ; DMA1 interrupt control register
ilvl0_dm1ic .btequ 0,dm1ic ; Interrupt priority level select bit
ilvl1_dm1ic .btequ 1,dm1ic ;
ilvl2_dm1ic .btequ 2,dm1ic ;
ir_dm1ic .btequ 3,dm1ic ; Interrupt request bit
;
kupic .equ 004dh ; Key input interrupt control register
ilvl0_kupic .btequ 0,kupic ; Interrupt priority level select bit
ilvl1_kupic .btequ 1,kupic ;
ilvl2_kupic .btequ 2,kupic ;
ir_kupic .btequ 3,kupic ; Interrupt request bit
;
adic .equ 004eh ; A-D interrupt control register
ilvl0_adic .btequ 0,adic ; Interrupt priority level select bit
ilvl1_adic .btequ 1,adic ;
ilvl2_adic .btequ 2,adic ;
ir_adic .btequ 3,adic ; Interrupt request bit
;
s2tic .equ 004fh ; UART2 transmit interrupt control register
ilvl0_s2tic .btequ 0,s2tic ; Interrupt priority level select bit
ilvl1_s2tic .btequ 1,s2tic ;
ilvl2_s2tic .btequ 2,s2tic ;
ir_s2tic .btequ 3,s2tic ; Interrupt request bit
;
s2ric .equ 0050h ; UART2 receive interrupt control register
ilvl0_s2ric .btequ 0,s2ric ; Interrupt priority level select bit
ilvl1_s2ric .btequ 1,s2ric ;
ilvl2_s2ric .btequ 2,s2ric ;
ir_s2ric .btequ 3,s2ric ; Interrupt request bit
;
s0tic .equ 0051h ; UART0 transmit interrupt control register
ilvl0_s0tic .btequ 0,s0tic ; Interrupt priority level select bit
ilvl1_s0tic .btequ 1,s0tic ;
ilvl2_s0tic .btequ 2,s0tic ;
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