vdsp_bak_testcoreb.ldf

OV7660驱动程序

/* MANAGED-BY-SYSTEM-BUILDER                                    */

/*
** ADSP-BF561 linker description file generated on Jun 30, 2008 at 14:56:11.
**
** Copyright (C) 2000-2007 Analog Devices Inc., All Rights Reserved.
**
** This file is generated automatically based upon the options selected
** in the LDF Wizard. Changes to the LDF configuration should be made by
** changing the appropriate options rather than editing this file.
**
** Configuration:-
**     crt_doj:                                .\Debug\testcoreb_basiccrt.doj
**     processor:                              ADSP-BF561
**     si_revision:                            automatic
**     cplb_init_cplb_ctrl:                    (
**                                              CPLB_ENABLE_ICACHE
**                                              CPLB_ENABLE_DCACHE
**                                              CPLB_ENABLE_CPLBS
**                                              CPLB_ENABLE_ICPLBS
**                                              CPLB_ENABLE_DCPLBS
**                                             )
**     cplb_init_dcache_ctrl:                  dcache_a_wt
**     cplb_init_cplb_src_file:                D:\MyProject\coreB\testcoreb_cplbtab.c
**     cplb_init_cplb_obj_file:                .\Debug\testcoreb_cplbtab.doj
**     using_cplusplus:                        true
**     mem_init:                               false
**     use_vdk:                                false
**     use_eh:                                 true
**     use_argv:                               false
**     running_from_internal_memory:           true
**     user_heap_src_file:                     D:\MyProject\coreB\testcoreb_heaptab.c
**     libraries_use_stdlib:                   true
**     libraries_use_fileio_libs:              false
**     libraries_use_ieeefp_emulation_libs:    false
**     libraries_use_eh_enabled_libs:          false
**     system_heap:                            L1
**     system_heap_min_size:                   2K
**     system_stack:                           L1
**     system_stack_min_size:                  2K
**     use_sdram:                              true
**     use_sdram_size:                         64M
**     use_sdram_partitioned:                  default
**     use_multicores:                         2
**     use_multicores_use_core:                coreB
**
*/

ARCHITECTURE(ADSP-BF561)

SEARCH_DIR($ADI_DSP/Blackfin/lib)


// Workarounds are enabled, exceptions are disabled.
#define RT_LIB_NAME(x) lib ## x ## y.dlb
#define RT_LIB_NAME_EH(x) lib ## x ## y.dlb
#define RT_LIB_NAME_MT(x) lib ## x ## y.dlb
#define RT_LIB_NAME_EH_MT(x) lib ## x ## y.dlb
#define RT_OBJ_NAME(x) x ## y.doj
#define RT_OBJ_NAME_MT(x) x ## mty.doj


#define LIBS \
   RT_LIB_NAME(small561) \
   ,RT_LIB_NAME_MT(io561) \
   ,RT_LIB_NAME_MT(c561) \
   ,RT_LIB_NAME_MT(event561) \
   ,RT_LIB_NAME_MT(x561) \
   ,RT_LIB_NAME_EH_MT(cpp561) \
   ,RT_LIB_NAME_EH_MT(cpprt561) \
   ,RT_LIB_NAME(f64ieee561) \
   ,RT_LIB_NAME(dsp561) \
   ,RT_LIB_NAME(sftflt561) \
   ,RT_LIB_NAME(etsi561) \
   ,RT_LIB_NAME(ssl561) \
   ,RT_LIB_NAME(drv561) \
   ,RT_LIB_NAME(usb561) \
   ,RT_LIB_NAME(rt_fileio561) \

$LIBS = LIBS;

/*$VDSG<insert-user-libraries-for-core-beginning>               */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-libraries-for-core-beginning>               */

$LIBRARIES_CORE_B = 
   $LIBS {!sharing("MustShare")}
   ;


/*$VDSG<insert-user-libraries-for-core-end>                     */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-libraries-for-core-end>                     */

$LIBRARIES_SHARED = 
   $LIBS

/*$VDSG<insert-user-libraries-shared>                           */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-libraries-shared>                           */

   ;

$OBJECTS_CORE_B = 

/*$VDSG<insert-user-objects-for-coreB-beginning>                */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-objects-for-coreB-beginning>                */

   ".\Debug\testcoreb_basiccrt.doj"
   , RT_LIB_NAME(profile561)
   , $COMMAND_LINE_OBJECTS {!DualCoreMem("CoreA")}
   , ".\Debug\testcoreb_cplbtab561b.doj"
   , RT_OBJ_NAME(crtn561)

/*$VDSG<insert-user-objects-for-coreB-end>                      */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-objects-for-coreB-end>                      */

   ;

$OBJS_LIBS_INTERNAL_CORE_B = 

/*$VDSG<insert-libraries-internal_coreB>                        */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-libraries-internal_coreB>                        */

   $OBJECTS_CORE_B{prefersMem("internal")}, $LIBRARIES_CORE_B{prefersMem("internal")}

/*$VDSG<insert-libraries-internal_coreB-end>                    */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-libraries-internal_coreB-end>                    */

   ;

$OBJS_LIBS_NOT_EXTERNAL_CORE_B = 

/*$VDSG<insert-libraries-not-external_coreB>                    */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-libraries-not-external_coreB>                    */

   $OBJECTS_CORE_B{!prefersMem("external")}, $LIBRARIES_CORE_B{!prefersMem("external")}

/*$VDSG<insert-libraries-not-external_coreB-end>                */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-libraries-not-external_coreB-end>                */

   ;


/*$VDSG<insert-user-macros>                                     */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-user-macros>                                     */


/*$VDSG<customise-async-macros>                                 */
/* This code is preserved if the LDF is re-generated.           */


#define ASYNC0_MEMTYPE RAM
#define ASYNC1_MEMTYPE RAM
#define ASYNC2_MEMTYPE RAM
#define ASYNC3_MEMTYPE RAM


/*$VDSG<customise-async-macros>                                 */


MEMORY
{
  /*
  ** ADSP-BF561 MEMORY MAP.
  **
  ** The known memory spaces are as follows:
  **
  ** 0xFFE00000 - 0xFFFFFFFF  Core MMR registers
  ** 0xFFC00000 - 0xFFDFFFFF  System MMR (Shared)
  ** 0xFFB01000 - 0xFFBFFFFF
  ** 0xFFB00000 - 0xFFB00FFF  Scratchpad
  ** 0xFFA14000 - 0xFFAF0000
  ** 0xFFA10000 - 0xFFA13FFF  Instr SR/Ca
  ** 0xFFA08000 - 0xFFA0FFFF
  ** 0xFFA04000 - 0xFFA07FFF
  ** 0xFFA00000 - 0xFFA03FFF  Instr SR
  ** 0xFF908000 - 0xFF9FFFFF
  ** 0xFF904000 - 0xFF907FFF  Bank B SR/Ca
  ** 0xFF900000 - 0xFF903FFF  Bank B SR
  ** 0xFF808000 - 0xFF8FFFFF
  ** 0xFF804000 - 0xFF807FFF  Bank A SR/Ca
  ** 0xFF800000 - 0xFF803FFF  Bank A SR
  ** 0xFF701000 - 0xFF7FFFFF
  ** 0xFF700000 - 0xFF700FFF  Scratchpad
  ** 0xFF614000 - 0xFF6FFFFF
  ** 0xFF610000 - 0xFF613FFF  Instr SR/Ca
  ** 0xFF608000 - 0xFF60FFFF
  ** 0xFF604000 - 0xFF607FFF
  ** 0xFF600000 - 0xFF603FFF  Instr SR
  ** 0xFF508000 - 0xFF5FFFFF
  ** 0xFF504000 - 0xFF507FFF  Bank B SR/Ca
  ** 0xFF500000 - 0xFF503FFF  Bank B SR
  ** 0xFF408000 - 0xFF4FFFFF
  ** 0xFF404000 - 0xFF407FFF  Bank A SR/Ca
  ** 0xFF400000 - 0xFF403FFF  Bank A SR
  ** 0xFEB20000 - 0xFF3FFFFF
  ** 0xFEB00000 - 0xFEB1FFFF  L2 Shared
  ** 0xEF004000 - 0xFEAFFFFF
  ** 0xEF002000 - 0xEF003FFF
  ** 0xEF001000 - 0xEF001FFF
  ** 0xEF000800 - 0xEF000FFF
  ** 0xEF000000 - 0xEF0007FF  Boot ROM
  ** 0x30000000 - 0xEEFFFFFF
  ** 0x2C000000 - 0x2FFFFFFF  Async 3
  ** 0x28000000 - 0x2BFFFFFF  Async 2
  ** 0x24000000 - 0x27FFFFFF  Async 1
  ** 0x20000000 - 0x23FFFFFF  Async 0
  ** 0x00000000 - 0x1FFFFFFF  SDRAM MEMORY (512MB)
  */
  
   MEM_L2_SRAM             { TYPE(RAM) START(0xFEB10000) END(0xFEB1FFFF) WIDTH(8) }
   MEM_ASYNC3              { TYPE(ASYNC3_MEMTYPE) START(0x2C000000) END(0x2FFFFFFF) WIDTH(8) }
   MEM_ASYNC2              { TYPE(ASYNC2_MEMTYPE) START(0x28000000) END(0x2BFFFFFF) WIDTH(8) }
   MEM_ASYNC1              { TYPE(ASYNC1_MEMTYPE) START(0x24000000) END(0x27FFFFFF) WIDTH(8) }
   MEM_ASYNC0              { TYPE(ASYNC0_MEMTYPE) START(0x20000000) END(0x23FFFFFF) WIDTH(8) }
   /* Maximum 256MB */
   MEM_SDRAM_BANK0         { TYPE(RAM) START(0x02000000) END(0x027fffff) WIDTH(8) } 
   MEM_SDRAM_BANK1         { TYPE(RAM) START(0x02800000) END(0x02ffffff) WIDTH(8) } 
   MEM_SDRAM_BANK2         { TYPE(RAM) START(0x03000000) END(0x037fffff) WIDTH(8) } 
   MEM_SDRAM_BANK3         { TYPE(RAM) START(0x03800000) END(0x03ffffff) WIDTH(8) } 
   
   /*$VDSG<insert-new-memory-segments>                          */
   /* Text inserted between these $VDSG comments will be preserved */
   MEM_L2_SRAM_SHARED      { TYPE(RAM) START(0xFEB0F000) END(0xFEB0FFFF) WIDTH(8) }
   /*$VDSG<insert-new-memory-segments>                          */
   
} /* MEMORY */

PROCESSOR p1
{
   
   MEMORY
   {
      MEM_L2_SRAM_B           { TYPE(RAM) START(0xFEB00000) END(0xFEB07FFF) WIDTH(8) }
      MEM_B_L1_SCRATCH        { TYPE(RAM) START(0xFF700000) END(0xFF700FFF) WIDTH(8) }
      MEM_B_L1_CODE_CACHE     { TYPE(RAM) START(0xFF610000) END(0xFF613FFF) WIDTH(8) }
      MEM_B_L1_CODE           { TYPE(RAM) START(0xFF600000) END(0xFF603FFF) WIDTH(8) }
      MEM_B_L1_DATA_B         { TYPE(RAM) START(0xFF500000) END(0xFF507FFF) WIDTH(8) }
      MEM_B_L1_DATA_A_CACHE   { TYPE(RAM) START(0xFF404000) END(0xFF407FFF) WIDTH(8) }
      MEM_B_L1_DATA_A         { TYPE(RAM) START(0xFF400000) END(0xFF403FFF) WIDTH(8) }
      
      /*$VDSG<insert-new-memory-segments-for-CORE-B>            */
      /* Text inserted between these $VDSG comments will be preserved */
      /*$VDSG<insert-new-memory-segments-for-CORE-B>            */
      
   } /* MEMORY */
   
   OUTPUT($COMMAND_LINE_OUTPUT_FILE)
   RESOLVE(start, 0xFF600000)

   /* Issue resolve statement for shared symbols mapped in CoreA.
   ** Below is an example of how to do that.
   */
#if defined(OTHERCORE)              /* OTHERCORE is a macro defined to name of CoreA DXE */
#  include "local_shared_symbols.h" /* C runtime shared symbols,
                                     * uses macro OTHERCORE.
                                     */
#if 0
                                    /* example resolve for user shared data */
   RESOLVE(_a_shared_datum, OTHERCORE)
#endif
#else
#warning OTHERCORE has not been defined. Shared symbols might not get resolved.
#warning Please consult Chapter 5 of the VisualDSP++ C/C++ Compiler and Libraries Manual.
#endif /* OTHERCORE */

   
   KEEP(start,_main)
   
   /*$VDSG<insert-user-ldf-commands-for-CORE-B>                 */
   /* Text inserted between these $VDSG comments will be preserved */
   /*$VDSG<insert-user-ldf-commands-for-CORE-B>                 */
   
   SECTIONS
   {
      /* Workaround for hardware errata 05-00-0189 and 05-00-0310 -
      ** "Speculative (and fetches made at boundary of reserved memory
      ** space) for instruction or data fetches may cause false
      ** protection exceptions" and "False hardware errors caused by
      ** fetches at the boundary of reserved memory ".
      **
      ** Done by avoiding use of 76 bytes from at the end of blocks
      ** that are adjacent to reserved memory. Workaround is enabled
      ** for appropriate silicon revisions (-si-revision switch).
      */
      RESERVE(___wabb1=MEMORY_END(MEM_B_L1_SCRATCH) - 75, ___lb1 = 76)
      RESERVE(___wabb2=MEMORY_END(MEM_B_L1_CODE_CACHE) - 75, ___l2 = 76)
      RESERVE(___wabb3=MEMORY_END(MEM_B_L1_CODE) - 75, ___l3 = 76)
      RESERVE(___wabb5=MEMORY_END(MEM_B_L1_DATA_B) - 75, ___l5 = 76)
      RESERVE(___waba6=MEMORY_END(MEM_B_L1_DATA_A_CACHE) - 75, ___l6 = 76)
      
      
      /*$VDSG<insert-new-sections-at-the-start-for-CORE-B>      */
      /* Text inserted between these $VDSG comments will be preserved */
      /*$VDSG<insert-new-sections-at-the-start-for-CORE-B>      */
      
      scratchpad
      {
         INPUT_SECTION_ALIGN(4)
         
         /*$VDSG<insert-input-sections-at-the-start-of-scratchpad-for-CORE-B>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-start-of-scratchpad-for-CORE-B>  */
         
      } > MEM_B_L1_SCRATCH