ov7660_coreb_cplbtab561b.c

OV7660驱动程序

   {0x29800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x29c00000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x2a000000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x2a400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x2a800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x2ac00000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x2b000000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x2b400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x2b800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x2bc00000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},

   // Async Memory Bank 1 (64MB)
   
   // CPLBs covering 64MB
   {0x24000000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x24400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x24800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x24c00000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x25000000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x25400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x25800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x25c00000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x26000000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x26400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x26800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x26c00000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x27000000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x27400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x27800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x27c00000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},

   // Async Memory Bank 0 (64MB)
   {0x20300000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)}, 
   
   // CPLBs covering 60MB
   {0x20400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x20800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x20c00000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x21000000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x21400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x21800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x21c00000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x22000000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x22400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x22800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x22c00000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x23000000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x23400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x23800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x23c00000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},

   // end of section - termination
   {0xffffffff, 0}, 
/*$VDSG<customizable-data-cplb-table>                           */


}; /* dcplbs_table */

#pragma section("cplb_data")
#pragma file_attr("DualCoreMem=CoreB")

cplb_entry icplbs_table[] = {



/*$VDSG<customizable-instr-cplb-table>                          */
/* This code is preserved if the CPLB tables are re-generated.  */


   // L1 Code
   {0xFF600000, (PAGE_SIZE_1MB | CPLB_I_PAGE_MGMT)}, 

   // L2 SRAM
   {0xFEB00000, (PAGE_SIZE_1MB | CPLB_IDOCACHE)}, 

   // Boot ROM
   {0xEF000000, (PAGE_SIZE_1KB | CPLB_I_PAGE_MGMT)}, 

   // Async Memory Bank 0
   {0x20000000, (PAGE_SIZE_1MB | CPLB_IDOCACHE)}, 

   // 512 MB (Maximum) SDRAM memory space (64 MB populated on Ez-kit)
   
   // CPLBs covering 64MB
   {0x00000000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x00400000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x00800000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x00c00000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x01000000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x01400000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x01800000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x01c00000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x02000000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x02400000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x02800000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x02c00000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x03000000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x03400000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x03800000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x03c00000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},

   // Async Memory Bank 3 (64MB)
   
   // CPLBs covering 64MB
   {0x2c000000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x2c400000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x2c800000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x2cc00000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x2d000000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x2d400000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x2d800000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x2dc00000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x2e000000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x2e400000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x2e800000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x2ec00000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x2f000000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x2f400000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x2f800000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x2fc00000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},

   // Async Memory Bank 2 (64MB)
   
   // CPLBs covering 64MB
   {0x28000000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x28400000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x28800000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x28c00000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x29000000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x29400000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x29800000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x29c00000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x2a000000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x2a400000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x2a800000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x2ac00000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x2b000000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x2b400000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x2b800000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x2bc00000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},

   // Async Memory Bank 1 (64MB)
   
   // CPLBs covering 64MB
   {0x24000000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x24400000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x24800000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x24c00000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x25000000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x25400000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x25800000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x25c00000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x26000000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x26400000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x26800000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x26c00000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x27000000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x27400000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x27800000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x27c00000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},

   // Async Memory Bank 0 (64MB)
   {0x20100000, (PAGE_SIZE_1MB | CPLB_IDOCACHE)}, 
   {0x20200000, (PAGE_SIZE_1MB | CPLB_IDOCACHE)}, 
   {0x20300000, (PAGE_SIZE_1MB | CPLB_IDOCACHE)}, 
   
   // CPLBs covering 60MB
   {0x20400000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x20800000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x20c00000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x21000000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x21400000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x21800000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x21c00000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x22000000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x22400000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x22800000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x22c00000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x23000000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x23400000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x23800000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x23c00000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},

   // end of section - termination
   {0xffffffff, 0}, 
/*$VDSG<customizable-instr-cplb-table>                          */


}; /* icplbs_table */



#ifdef _MISRA_RULES
#pragma diag(pop)
#endif /* _MISRA_RULES */