ov7660_coreb_cplbtab561b.c

OV7660驱动程序

/* MANAGED-BY-SYSTEM-BUILDER                                    */

/*
** CPLB table definitions for coreB generated on Sep 24, 2008 at 18:40:28.
**
** Copyright (C) 2000-2008 Analog Devices Inc., All Rights Reserved.
**
** This file is generated automatically based upon the options selected
** in the LDF Wizard. Changes to the LDF configuration should be made by
** changing the appropriate options rather than editing this file.
**
** Configuration:-
**     crt_doj:                                .\Debug\ov7660_coreb_basiccrt.doj
**     processor:                              ADSP-BF561
**     si_revision:                            0.3
**     cplb_init_cplb_ctrl:                    123
**     cplb_init_dcache_ctrl:                  dcache_a_wt
**     cplb_init_cplb_src_file:                D:\MyProject\OV7660_coreB\ov7660_coreb_cplbtab.c
**     cplb_init_cplb_obj_file:                .\Debug\ov7660_coreb_cplbtab.doj
**     using_cplusplus:                        true
**     mem_init:                               false
**     use_vdk:                                false
**     use_eh:                                 true
**     use_argv:                               false
**     running_from_internal_memory:           true
**     user_heap_src_file:                     D:\MyProject\OV7660_coreB\ov7660_coreb_heaptab.c
**     libraries_use_stdlib:                   true
**     libraries_use_fileio_libs:              false
**     libraries_use_ieeefp_emulation_libs:    false
**     libraries_use_eh_enabled_libs:          false
**     system_heap:                            L1
**     system_heap_min_size:                   2k
**     system_stack:                           L1
**     system_stack_min_size:                  2k
**     use_sdram:                              true
**     use_sdram_size:                         32M
**     use_sdram_partitioned:                  default
**     use_multicores:                         2
**     use_multicores_use_core:                coreB
**
*/


#ifdef _MISRA_RULES
#pragma diag(push)
#pragma diag(suppress:misra_rule_2_2)
#pragma diag(suppress:misra_rule_8_10)
#pragma diag(suppress:misra_rule_10_1_a)
#endif /* _MISRA_RULES */



#define CACHE_MEM_MODE CPLB_DDOCACHE_WT



#include <sys/platform.h>
#include <cplbtab.h>

#pragma section("cplb_data")
#pragma file_attr("DualCoreMem=CoreB")

cplb_entry dcplbs_table[] = {



/*$VDSG<customizable-data-cplb-table>                           */
/* This code is preserved if the CPLB tables are re-generated.  */


   // L1 Data A & B, (set write-through bit to avoid 1st write exceptions)
   {0xFF400000, (PAGE_SIZE_4MB | CPLB_DNOCACHE | CPLB_LOCK | CPLB_WT)}, 

   // L2 SRAM
   {0xFEB00000, (PAGE_SIZE_4KB | CPLB_D_PAGE_MGMT | CPLB_WT)}, 
   {0xFEB01000, (PAGE_SIZE_4KB | CACHE_MEM_MODE)}, 
   {0xFEB02000, (PAGE_SIZE_4KB | CACHE_MEM_MODE)}, 
   {0xFEB03000, (PAGE_SIZE_4KB | CACHE_MEM_MODE)}, 
   {0xFEB04000, (PAGE_SIZE_4KB | CACHE_MEM_MODE)}, 
   {0xFEB05000, (PAGE_SIZE_4KB | CACHE_MEM_MODE)}, 
   {0xFEB06000, (PAGE_SIZE_4KB | CACHE_MEM_MODE)}, 
   {0xFEB07000, (PAGE_SIZE_4KB | CACHE_MEM_MODE)}, 
   {0xFEB08000, (PAGE_SIZE_4KB | CACHE_MEM_MODE)}, 
   {0xFEB09000, (PAGE_SIZE_4KB | CACHE_MEM_MODE)}, 
   {0xFEB0a000, (PAGE_SIZE_4KB | CACHE_MEM_MODE)}, 
   {0xFEB0b000, (PAGE_SIZE_4KB | CACHE_MEM_MODE)}, 
   {0xFEB0c000, (PAGE_SIZE_4KB | CACHE_MEM_MODE)}, 
   {0xFEB0d000, (PAGE_SIZE_4KB | CACHE_MEM_MODE)}, 
   {0xFEB0e000, (PAGE_SIZE_4KB | CACHE_MEM_MODE)}, 
   {0xFEB0f000, (PAGE_SIZE_4KB | CACHE_MEM_MODE)}, 

   // L2 SRAM, disabling cache for memory that may contain shared data
   {0xFEB10000, (PAGE_SIZE_4KB | CPLB_DNOCACHE)}, 
   {0xFEB11000, (PAGE_SIZE_4KB | CPLB_DNOCACHE)}, 
   {0xFEB12000, (PAGE_SIZE_4KB | CPLB_DNOCACHE)}, 
   {0xFEB13000, (PAGE_SIZE_4KB | CPLB_DNOCACHE)}, 
   {0xFEB14000, (PAGE_SIZE_4KB | CPLB_DNOCACHE)}, 
   {0xFEB15000, (PAGE_SIZE_4KB | CPLB_DNOCACHE)}, 
   {0xFEB16000, (PAGE_SIZE_4KB | CPLB_DNOCACHE)}, 
   {0xFEB17000, (PAGE_SIZE_4KB | CPLB_DNOCACHE)}, 
   {0xFEB18000, (PAGE_SIZE_4KB | CPLB_DNOCACHE)}, 
   {0xFEB19000, (PAGE_SIZE_4KB | CPLB_DNOCACHE)}, 
   {0xFEB1a000, (PAGE_SIZE_4KB | CPLB_DNOCACHE)}, 
   {0xFEB1b000, (PAGE_SIZE_4KB | CPLB_DNOCACHE)}, 
   {0xFEB1c000, (PAGE_SIZE_4KB | CPLB_DNOCACHE)}, 
   {0xFEB1d000, (PAGE_SIZE_4KB | CPLB_DNOCACHE)}, 
   {0xFEB1e000, (PAGE_SIZE_4KB | CPLB_DNOCACHE)}, 
   {0xFEB1f000, (PAGE_SIZE_4KB | CPLB_DNOCACHE)}, 

   // Async Memory Bank 2 (Second)
   // Async Memory Bank 1 (Prim B)
   // Async Memory Bank 0 (Prim A) 
   {0x20200000, (PAGE_SIZE_1MB | CPLB_DNOCACHE)}, 
   {0x20100000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)}, 
   {0x20000000, (PAGE_SIZE_1MB | CPLB_DNOCACHE)}, 

   // 512 MB (Maximum) SDRAM memory space (64 MB populated on Ez-kit)
   
   // CPLBs covering 32MB
   {0x00000000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
   {0x00100000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
   {0x00200000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
   {0x00300000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
   {0x00400000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
   {0x00500000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
   {0x00600000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
   {0x00700000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
   {0x00800000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
   {0x00900000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
   {0x00a00000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
   {0x00b00000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
   {0x00c00000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
   {0x00d00000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
   {0x00e00000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
   {0x00f00000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
   {0x01000000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
   {0x01100000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
   {0x01200000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
   {0x01300000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
   {0x01400000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
   {0x01500000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
   {0x01600000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
   {0x01700000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
   {0x01800000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
   {0x01900000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
   {0x01a00000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
   {0x01b00000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
   {0x01c00000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
   {0x01d00000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
   {0x01e00000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
   {0x01f00000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
   {0x02000000, (PAGE_SIZE_4MB | CACHE_MEM_MODE | CPLB_LOCK)}, 
   {0x02400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE | CPLB_LOCK)}, 
   
   // CPLBs covering 56MB
   {0x02800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x02c00000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x03000000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x03400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x03800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x03c00000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x04000000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x04400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x04800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x04c00000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x05000000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x05400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x05800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x05c00000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},

   // Async Memory Bank 3 (64MB)
   
   // CPLBs covering 64MB
   {0x2c000000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x2c400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x2c800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x2cc00000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x2d000000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x2d400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x2d800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x2dc00000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x2e000000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x2e400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x2e800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x2ec00000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x2f000000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x2f400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x2f800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x2fc00000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},

   // Async Memory Bank 2 (64MB)
   
   // CPLBs covering 64MB
   {0x28000000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x28400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x28800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x28c00000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x29000000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x29400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},