vdsp_bak_ov7660_coreb.ldf

OV7660驱动程序

      L1_code
      {
         INPUT_SECTION_ALIGN(4)
         __CORE = 1;
         INPUT_SECTIONS($OBJECTS_CORE_B(L1_code) $LIBRARIES_CORE_B(L1_code))
         
         /*$VDSG<insert-input-sections-at-the-start-of-l1_code_coreB>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-start-of-l1_code_coreB>  */
         
         INPUT_SECTIONS($OBJECTS_CORE_B(VDK_ISR_code) $LIBRARIES_CORE_B(VDK_ISR_code))
         INPUT_SECTIONS($OBJECTS_CORE_B(cplb) $LIBRARIES_CORE_B(cplb))
         INPUT_SECTIONS($OBJECTS_CORE_B(cplb_code) $LIBRARIES_CORE_B(cplb_code))
         INPUT_SECTIONS($OBJECTS_CORE_B(noncache_code) $LIBRARIES_CORE_B(noncache_code))
         INPUT_SECTIONS($OBJECTS_CORE_B(program) $LIBRARIES_CORE_B(program))
         
         /*$VDSG<insert-input-sections-at-the-end-of-l1_code_coreB>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-end-of-l1_code_coreB>  */
         
      } > MEM_B_L1_CODE

      L1_code_cache
      {
         INPUT_SECTION_ALIGN(4)
         ___l1_code_cache = 1;
      } > MEM_B_L1_CODE_CACHE

      L1_data_a_cache
      {
         INPUT_SECTION_ALIGN(4)
         ___l1_data_cache_a = 1;
      } > MEM_B_L1_DATA_A_CACHE

      L1_data_a_1
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS($OBJECTS_CORE_B(L1_data_a) $LIBRARIES_CORE_B(L1_data_a))
         
         /*$VDSG<insert-input-sections-at-the-start-of-l1_data_a_coreB>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-start-of-l1_data_a_coreB>  */
         
         RESERVE(heaps_and_stack_in_L1_data_a, heaps_and_stack_in_L1_data_a_length = 2K,4)
      } > MEM_B_L1_DATA_A

      L1_data_a_bsz ZERO_INIT
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS( $OBJECTS_CORE_B(L1_bsz) $LIBRARIES_CORE_B(L1_bsz))
      } > MEM_B_L1_DATA_A

      L1_data_a
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS($OBJECTS_CORE_B{DualCoreMem("CoreB")}(cplb_data) $LIBRARIES_CORE_B{DualCoreMem("CoreB")}(cplb_data))
         INPUT_SECTIONS($OBJECTS_CORE_B(cplb_data) $LIBRARIES_CORE_B(cplb_data))
         INPUT_SECTIONS($OBJECTS_CORE_B(voldata) $LIBRARIES_CORE_B(voldata))
         INPUT_SECTIONS($OBJECTS_CORE_B(constdata) $LIBRARIES_CORE_B(constdata))
         INPUT_SECTIONS($OBJS_LIBS_INTERNAL_CORE_B(data1))
         INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL_CORE_B(data1))
         INPUT_SECTIONS($OBJECTS_CORE_B(data1) $LIBRARIES_CORE_B(data1))
         INPUT_SECTIONS($OBJECTS_CORE_B(.edt) $LIBRARIES_CORE_B(.edt))
         INPUT_SECTIONS($OBJECTS_CORE_B(.cht) $LIBRARIES_CORE_B(.cht))
         
         /*$VDSG<insert-input-sections-at-the-end-of-l1_data_a_coreB>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-end-of-l1_data_a_coreB>  */
         
      } > MEM_B_L1_DATA_A

      bsz_L1_data_a ZERO_INIT
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS($OBJS_LIBS_INTERNAL_CORE_B(bsz))
         INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL_CORE_B(bsz))
         INPUT_SECTIONS($OBJECTS_CORE_B(bsz) $LIBRARIES_CORE_B(bsz))
      } > MEM_B_L1_DATA_A

      L1_data_a_stack_heap
      {
         INPUT_SECTION_ALIGN(4)
         RESERVE_EXPAND(heaps_and_stack_in_L1_data_a, heaps_and_stack_in_L1_data_a_length , 0, 4)
         ldf_heap_space = heaps_and_stack_in_L1_data_a;
         ldf_heap_end = (ldf_heap_space + (heaps_and_stack_in_L1_data_a_length - 4)) &0xfffffffc;
         ldf_heap_length = ldf_heap_end - ldf_heap_space;
      } > MEM_B_L1_DATA_A

      L1_data_b_bsz ZERO_INIT
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS( $OBJECTS_CORE_B(L1_bsz) $LIBRARIES_CORE_B(L1_bsz))
      } > MEM_B_L1_DATA_B

      L1_data_b_tables
      {
         INPUT_SECTION_ALIGN(4)
         FORCE_CONTIGUITY
         INPUT_SECTIONS($OBJECTS_CORE_B(ctor) $LIBRARIES_CORE_B(ctor))
         INPUT_SECTIONS($OBJECTS_CORE_B(ctorl) $LIBRARIES_CORE_B(ctorl))
         INPUT_SECTIONS($OBJECTS_CORE_B(vtbl) $LIBRARIES_CORE_B(vtbl))
         INPUT_SECTIONS($OBJECTS_CORE_B(.gdt) $LIBRARIES_CORE_B(.gdt))
         INPUT_SECTIONS($OBJECTS_CORE_B(.gdtl) $LIBRARIES_CORE_B(.gdtl))
         INPUT_SECTIONS($OBJECTS_CORE_B(.frt) $LIBRARIES_CORE_B(.frt))
         INPUT_SECTIONS($OBJECTS_CORE_B(.rtti) $LIBRARIES_CORE_B(.rtti))
         INPUT_SECTIONS($OBJECTS_CORE_B(.edt) $LIBRARIES_CORE_B(.edt))
         INPUT_SECTIONS($OBJECTS_CORE_B(.cht) $LIBRARIES_CORE_B(.cht))
      } > MEM_B_L1_DATA_B

      L1_data_b
      {
         INPUT_SECTION_ALIGN(4)
         ___l1_data_cache_b = 0;
         INPUT_SECTIONS($OBJECTS_CORE_B(L1_data_b) $LIBRARIES_CORE_B(L1_data_b))
         
         /*$VDSG<insert-input-sections-at-the-start-of-l1_data_b_coreB>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-start-of-l1_data_b_coreB>  */
         
         RESERVE(heaps_and_stack_in_L1_data_b, heaps_and_stack_in_L1_data_b_length = 2K,4)
         INPUT_SECTIONS($OBJS_LIBS_INTERNAL_CORE_B(data1))
         INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL_CORE_B(data1))
         INPUT_SECTIONS($OBJECTS_CORE_B(data1) $LIBRARIES_CORE_B(data1))
         INPUT_SECTIONS($OBJECTS_CORE_B{DualCoreMem("CoreB")}(cplb_data) $LIBRARIES_CORE_B{DualCoreMem("CoreB")}(cplb_data))
         INPUT_SECTIONS($OBJECTS_CORE_B(cplb_data) $LIBRARIES_CORE_B(cplb_data))
         INPUT_SECTIONS($OBJECTS_CORE_B(voldata) $LIBRARIES_CORE_B(voldata))
         INPUT_SECTIONS($OBJECTS_CORE_B(constdata) $LIBRARIES_CORE_B(constdata))
         
         /*$VDSG<insert-input-sections-at-the-end-of-l1_data_b_coreB>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-end-of-l1_data_b_coreB>  */
         
      } > MEM_B_L1_DATA_B

      bsz_L1_data_b ZERO_INIT
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS($OBJS_LIBS_INTERNAL_CORE_B(bsz))
         INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL_CORE_B(bsz))
         INPUT_SECTIONS($OBJECTS_CORE_B(bsz) $LIBRARIES_CORE_B(bsz))
      } > MEM_B_L1_DATA_B

      L1_data_b_stack_heap
      {
         INPUT_SECTION_ALIGN(4)
         RESERVE_EXPAND(heaps_and_stack_in_L1_data_b, heaps_and_stack_in_L1_data_b_length , 0, 4)
         ldf_stack_space = heaps_and_stack_in_L1_data_b;
         ldf_stack_end = (ldf_stack_space + (heaps_and_stack_in_L1_data_b_length - 4)) &0xfffffffc;
      } > MEM_B_L1_DATA_B

      L2_sram_b
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS($OBJECTS_CORE_B(L2_sram) $LIBRARIES_CORE_B(L2_sram))
         INPUT_SECTIONS($OBJECTS_CORE_B(l2_sram) $LIBRARIES_CORE_B(l2_sram))
         INPUT_SECTIONS($OBJECTS_CORE_B(VDK_ISR_code) $LIBRARIES_CORE_B(VDK_ISR_code))
         
         /*$VDSG<insert-input-sections-at-the-start-of-L2_sram_b>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-start-of-L2_sram_b>  */
         
         INPUT_SECTIONS($OBJECTS_CORE_B(noncache_code) $LIBRARIES_CORE_B(noncache_code))
         INPUT_SECTIONS($OBJECTS_CORE_B(program) $LIBRARIES_CORE_B(program))
         INPUT_SECTIONS($OBJECTS_CORE_B(cplb) $LIBRARIES_CORE_B(cplb))
         INPUT_SECTIONS($OBJECTS_CORE_B(cplb_code) $LIBRARIES_CORE_B(cplb_code))
         INPUT_SECTIONS($OBJECTS_CORE_B(data1) $LIBRARIES_CORE_B(data1))
         INPUT_SECTIONS($OBJECTS_CORE_B(voldata) $LIBRARIES_CORE_B(voldata))
         INPUT_SECTIONS($OBJECTS_CORE_B{DualCoreMem("CoreB")}(cplb_data) $LIBRARIES_CORE_B{DualCoreMem("CoreB")}(cplb_data))
         INPUT_SECTIONS($OBJECTS_CORE_B(cplb_data) $LIBRARIES_CORE_B(cplb_data))
         INPUT_SECTIONS($OBJECTS_CORE_B(.edt) $LIBRARIES_CORE_B(.edt))
         INPUT_SECTIONS($OBJECTS_CORE_B(.cht) $LIBRARIES_CORE_B(.cht))
         INPUT_SECTIONS($OBJECTS_CORE_B(constdata) $LIBRARIES_CORE_B(constdata))
         
         /*$VDSG<insert-input-sections-at-the-end-of-L2_sram_b>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-end-of-L2_sram_b>  */
         
      } > MEM_L2_SRAM_B

      bsz_L2_sram_b ZERO_INIT
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS($OBJECTS_CORE_B(bsz) $LIBRARIES_CORE_B(bsz))
      } > MEM_L2_SRAM_B

      L2_sram_b_stack_heap
      {
         INPUT_SECTION_ALIGN(4)
      } > MEM_L2_SRAM_B

      sdram_bank0
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS($OBJECTS_CORE_B(sdram_data_bank0) $LIBRARIES_CORE_B(sdram_data_bank0))
         INPUT_SECTIONS($OBJECTS_CORE_B(sdram_bank0) $LIBRARIES_CORE_B(sdram_bank0))
         INPUT_SECTIONS($OBJECTS_CORE_B(program) $LIBRARIES_CORE_B(program))
         INPUT_SECTIONS($OBJECTS_CORE_B(noncache_code) $LIBRARIES_CORE_B(noncache_code))
         
         /*$VDSG<insert-input-sections-at-the-end-of-sdram0_bank0>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-end-of-sdram0_bank0>  */
         
      } > MEM_SDRAM_BANK0

      sdram_bank1
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS($OBJECTS_CORE_B(sdram_bank1) $LIBRARIES_CORE_B(sdram_bank1))
         INPUT_SECTIONS($OBJECTS_CORE_B(sdram_data_bank1) $LIBRARIES_CORE_B(sdram_data_bank1))
         INPUT_SECTIONS($OBJECTS_CORE_B(data1) $LIBRARIES_CORE_B(data1))
         INPUT_SECTIONS($OBJECTS_CORE_B(voldata) $LIBRARIES_CORE_B(voldata))
         
         /*$VDSG<insert-input-sections-at-the-end-of-sdram_bank1>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-end-of-sdram_bank1>  */
         
      } > MEM_SDRAM_BANK1

      sdram_bank2
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS($OBJECTS_CORE_B(sdram_data_bank2) $LIBRARIES_CORE_B(sdram_data_bank2))
         INPUT_SECTIONS($OBJECTS_CORE_B(sdram_bank2) $LIBRARIES_CORE_B(sdram_bank2))
         INPUT_SECTIONS($OBJECTS_CORE_B(program) $LIBRARIES_CORE_B(program))
         INPUT_SECTIONS($OBJECTS_CORE_B(noncache_code) $LIBRARIES_CORE_B(noncache_code))
         
         /*$VDSG<insert-input-sections-at-the-end-of-sdram_bank2>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-end-of-sdram_bank2>  */
         
      } > MEM_SDRAM_BANK2

      sdram_bank3
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS($OBJECTS_CORE_B(sdram_data_bank3) $LIBRARIES_CORE_B(sdram_data_bank3))
         INPUT_SECTIONS($OBJECTS_CORE_B(sdram_bank3) $LIBRARIES_CORE_B(sdram_bank3))
         INPUT_SECTIONS($OBJECTS_CORE_B(data1) $LIBRARIES_CORE_B(data1))
         INPUT_SECTIONS($OBJECTS_CORE_B(voldata) $LIBRARIES_CORE_B(voldata))
         
         /*$VDSG<insert-input-sections-at-the-end-of-sdram_bank3>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-end-of-sdram_bank3>  */
         
      } > MEM_SDRAM_BANK3

      sdram_bank3_1
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS($OBJECTS_CORE_B(sdram_data_bank3) $LIBRARIES_CORE_B(sdram_data_bank3))
         INPUT_SECTIONS($OBJECTS_CORE_B(constdata) $LIBRARIES_CORE_B(constdata))
         
         /*$VDSG<insert-input-sections-at-the-end-of-sdram_bank3_1>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-end-of-sdram_bank3_1>  */
         
      } > MEM_SDRAM_BANK3

      sdram_bank3_bsz ZERO_INIT
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS($OBJECTS_CORE_B(sdram_bsz) $LIBRARIES_CORE_B(sdram_bsz))
         INPUT_SECTIONS($OBJECTS_CORE_B(bsz) $LIBRARIES_CORE_B(bsz))
         
         /*$VDSG<insert-input-sections-at-the-end-of-sdram_bank3_bsz>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-end-of-sdram_bank3_bsz>  */
         
      } > MEM_SDRAM_BANK3

      sdram_bank3_2
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS($OBJECTS_CORE_B(sdram_bank3) $LIBRARIES_CORE_B(sdram_bank3))
         INPUT_SECTIONS($OBJECTS_CORE_B(VDK_ISR_code) $LIBRARIES_CORE_B(VDK_ISR_code))
         INPUT_SECTIONS($OBJECTS_CORE_B(program) $LIBRARIES_CORE_B(program))
         INPUT_SECTIONS($OBJECTS_CORE_B(noncache_code) $LIBRARIES_CORE_B(noncache_code))
         
         /*$VDSG<insert-input-sections-at-the-end-of-sdram_bank3_2>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-end-of-sdram_bank3_2>  */
         
      } > MEM_SDRAM_BANK3

      sdram_bank3_3
      {
         INPUT_SECTION_ALIGN(4)
         
         /*$VDSG<insert-input-sections-at-the-start-of-sdram_bank3_3>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-start-of-sdram_bank3_3>  */
         
         INPUT_SECTIONS($OBJECTS_CORE_B(sdram_data_bank3) $LIBRARIES_CORE_B(sdram_data_bank3))
         INPUT_SECTIONS($OBJECTS_CORE_B(constdata) $LIBRARIES_CORE_B(constdata))
      } > MEM_SDRAM_BANK3

      
      /*$VDSG<insert-new-sections-at-the-end-for-CORE-B>        */
      /* Text inserted between these $VDSG comments will be preserved */
     
         shared_l2 
      {
         INPUT_SECTION_ALIGN(4)
         INPUT_SECTIONS($OBJECTS_CORE_B(primio_atomic_lock) $LIBRARIES_SHARED(primio_atomic_lock))
      } > MEM_L2_SRAM_SHARED     
          /*$VDSG<insert-new-sections-at-the-end-for-CORE-B>        */

   } /* SECTIONS */
} /* p1 */